Rainbow Electronics AT89C51SND1C - Manual (Page 97)

97
AT8xC51SND1C
4109E–8051–06/03
USB Interrupt System
Interrupt System Priorities Figure 68. USB Interrupt Control System
Table 1. Priority Levels
USB Interrupt Control System As shown in Figure 69, many events can produce a USB interrupt:
• TXCMPL: Transmitted In Data (Table 96 on page 103). This bit is set by hardware
when the Host accept a In packet.
• RXOUTB0: Received Out Data Bank 0 (Table 96 on page 103). This bit is set by
hardware when an Out packet is accepted by the endpoint and stored in bank 0.
• RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints) (Table 96 on
page 103). This bit is set by hardware when an Out packet is accepted by the
endpoint and stored in bank 1.
• RXSETUP: Received Setup (Table 96 on page 103). This bit is set by hardware
when an SETUP packet is accepted by the endpoint.
• STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (Table 96 on
page 103). This bit is set by hardware when a STALL handshake has been sent as
requested by STALLRQ, and is reset by hardware when a SETUP packet is
received.
• SOFINT: Start of Frame Interrupt (Table 92 on page 100). This bit is set by hardware
when a USB start of frame packet has been received.
• WUPCPU: Wake-Up CPU Interrupt (Table 92 on page 100). This bit is set by
hardware when a USB resume is detected on the USB bus, after a SUSPEND state.
• SPINT: Suspend Interrupt (Table 92 on page 100). This bit is set by hardware when
a USB suspend is detected on the USB bus.
EUSB
IE1.6
EA
IE0.7
USB
Controller
IPH/L
Interrupt Enable Lowest Priority Interrupts Priority Enable
00
01
10
11
D+
D-
IPHUSB IPLUSB USB Priority Level
0 0 0..................Lowest
0 1 1
1 0 2
1 1 3..................Highest