Rainbow Electronics AT89C51SND1C - Manual (Page 86)

86
AT8xC51SND1C
4109E–8051–06/03
• Endpoint FIFO reset
Before using an endpoint, its FIFO should be reset. This action resets the FIFO
pointer to its original value, resets the Byte counter of the endpoint (UBYCTX regis-
ter), and resets the data toggle bit (DTGL bit in UEPCONX).
The reset of an endpoint FIFO is performed by setting to 1 and resetting to 0 the
corresponding bit in the UEPRST register.
For example, in order to reset the Endpoint number 2 FIFO, write 0000 0100b then
0000 0000b in the UEPRST register.
Note that the endpoint reset doesn’t reset the bank number for ping-pong endpoints.
Read/Write Data FIFO
Read Data FIFO The read access for each OUT endpoint is performed using the UEPDATX register.
After a new valid packet has been received on an Endpoint, the data are stored into the
FIFO and the Byte counter of the endpoint is updated (UBYCTX registers). The firmware
has to store the endpoint Byte counter before any access to the endpoint FIFO. The
Byte counter is not updated when reading the FIFO.
To read data from an endpoint, select the correct endpoint number in UEPNUM and
read the UEPDATX register. This action automatically decreases the corresponding
address vector, and the next data is then available in the UEPDATX register.
Write Data FIFO The write access for each IN endpoint is performed using the UEPDATX register.
To write a Byte into an IN endpoint FIFO, select the correct endpoint number in UEP-
NUM and write into the UEPDATX register. The corresponding address vector is
automatically increased, and another write can be carried out.
Warning 1: The Byte counter is not updated.
Warning 2: Do not write more Bytes than supported by the corresponding endpoint.
FIFO Mapping
Figure 61. Endpoint FIFO Configuration
UEPNUM
Endpoint 0
Endpoint 2
UEPSTA0 UEPCON0 UEPDAT0
UEPSTA2 UEPCON2 UEPDAT2
0
1
2
SFR Registers
UEPSTAX UEPCONX UEPDATX X
UBYCT0
UBYCT2
UBYCTX