Rainbow Electronics AT89C51SND1C - Manual (Page 153)

153
AT8xC51SND1C
4109E–8051–06/03
Master Mode with Interrupt Figure 120 shows the initialization phase and the transfer phase flows using the inter-
rupt. Using this flow prevents any overrun error occurrence.
The bit rate is selected according to Table 131.
The transfer format depends on the slave peripheral.
SS may be deasserted between transfers depending also on the slave peripheral.
Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag.
Clear is effective when reading SPDAT.
Figure 120. Master SPI Interrupt Flows
SPI Initialization
Interrupt Policy
Enable interrupt
ESPI =1
SPI Interrupt
Service Routine
Select Master Mode
MSTR = 1
Select Bit Rate
program SPR2:0
Select Format
program CPOL & CPHA
Enable SPI
SPEN = 1
Read Status
Read SPSTA
Start New Transfer
write data in SPDAT
Last Transfer?
Get Data Received
read SPDAT
Disable interrupt
SPIE = 0
Select Slave
Pn.x = L
Start Transfer
write data in SPDAT
Deselect Slave
Pn.x = H