Texas Instruments TMS320C64x DSP - Manual (Page 305)

Index
Index-9 SPRU629
video capture channel B vertical interrupt register
(VCBVINT) 3-63
video capture FIFO configurations 1-6
video capture mode
BT.656 3-3
raw data 3-32
TSI 3-37
Y/C 3-12
video display
counters 4-5
external sync operation 4-8
FIFO configurations 1-9
FIFO overrun 4-51
FIFO registers 4-96
image timing 4-2
mode selection 4-2
port sync operation 4-8
registers 4-52
recommended values 4-94
signal mapping 1-14
sync signal generation 4-7
throughput 2-15
video display clipping register (VDCLIP) 4-85
video display control register (VDCTL) 4-55
video display counter reload register
(VDRELOAD) 4-83
video display default display value register
(VDDEFVAL) 4-86
video display display event register
(VDDISPEVT) 4-84
video display field 1 image offset register
(VDIMGOFF1) 4-68
video display field 1 image size register
(VDIMGSZ1) 4-70
video display field 1 timing register
(VDFLDT1) 4-74
video display field 1 vertical blanking bit register
(VDVBIT1) 4-90
video display field 1 vertical blanking end register
(VDVBLKE1) 4-64
video display field 1 vertical blanking start register
(VDVBLKS1) 4-62
video display field 1 vertical synchronization end
register (VDVSYNE1) 4-80
video display field 1 vertical synchronization start
register (VDVSYNS1) 4-79
video display field 2 image offset register
(VDIMGOFF2) 4-71
video display field 2 image size register
(VDIMGSZ2) 4-73
video display field 2 timing register
(VDFLDT2) 4-75
video display field 2 vertical blanking bit register
(VDVBIT2) 4-92
video display field 2 vertical blanking end register
(VDVBLKE2) 4-67
video display field 2 vertical blanking start register
(VDVBLKS2) 4-65
video display field 2 vertical synchronization end
register (VDVSYNE2) 4-82
video display field 2 vertical synchronization start
register (VDVSYNS2) 4-81
video display field bit register (VDFBIT) 4-89
video display FIFO configurations 1-9
video display frame size register (VDFRMSZ) 4-60
video display horizontal blanking register
(VDHBLNK) 4-61
video display horizontal synchronization register
(VDHSYNC) 4-78
video display mode
BT.656 4-9
display selection 4-31
display timing examples 4-35
field and frame operation 4-30
raw data 4-25
Y/C 4-16
video display status register (VDSTAT) 4-53
video display threshold register (VDTHRLD) 4-76
video display vertical interrupt register
(VDVINT) 4-88
video input filtering 3-26
video output filtering 4-21
video port
block diagram 1-4
clocks 2-12
control registers 2-16
DMA interface 1-5
DMA operation 2-6
FIFO configurations 1-5
interrupt operation 2-5
operating mode selection 2-19
overview 1-2
pin mapping 1-13
reset operation 2-2
throughput and latency 2-13
video port control register (VPCTL) 2-17