Texas Instruments TMS320C64x DSP - Manual (Page 250)

GPIO Registers
5-9 General Purpose I/O Operation SPRU629
Table 5–5. Video Port Pin Direction Register (PDIR) Field Descriptions (Continued)
Bit Description Value symval † field †
21 PDIR21 PDIR21 bit controls the direction of the VCTL2 pin.
VCTL2IN 0 Pin functions as input.
VCTL2OUT 1 Pin functions as output.
20 PDIR20 PDIR20 bit controls the direction of the VCTL1 pin.
VCTL1IN 0 Pin functions as input.
VCTL1OUT 1 Pin functions as output.
19–17 Reserved – 0 Reserved. The reserved bit location is always read as 0.
A value written to this field has no effect.
16 PDIR16 PDIR16 bit controls the direction of the VDATA[19–16]
pins.
VDATA16TO19IN 0 Pins function as input.
VDATA16TO19OUT 1 Pins function as output.
15–13 Reserved – 0 Reserved. The reserved bit location is always read as 0.
A value written to this field has no effect.
12 PDIR12 PDIR12 bit controls the direction of the VDATA[15–12]
pins.
VDATA12TO15IN 0 Pins function as input.
VDATA12TO15OUT 1 Pins function as output.
11 Reserved – 0 Reserved. The reserved bit location is always read as 0.
A value written to this field has no effect.
10 PDIR10 PDIR10 bit controls the direction of the VDATA[11–10]
pins.
VDATA10TO11IN 0 Pins function as input.
VDATA10TO11OUT 1 Pins function as output.
9 Reserved – 0 Reserved. The reserved bit location is always read as 0.
A value written to this field has no effect.
† For CSL implementation, use the notation VP_PDIR_field_symval