Texas Instruments TMS320C64x DSP - Manual (Page 302)

Index
Index-6 SPRU629
registers (continued)
video display
frame size register (VDFRMSZ) 4-60
horizontal blanking register
(VDHBLNK) 4-61
horizontal synchronization register
(VDHSYNC) 4-78
recommended values 4-94
status register (VDSTAT) 4-53
threshold register (VDTHRLD) 4-76
vertical interrupt register (VDVINT) 4-88
Y FIFO destination register A (YDSTA) 4-96
Y FIFO destination register B (YDSTB) 4-96
video port 2-16
control register (VPCTL) 2-17
interrupt enable register (VPIE) 2-21
interrupt status register (VPIS) 2-24
peripheral control register (PCR) 5-4
peripheral identification register (VPPID) 5-3
pin data clear register (PDCLR) 5-17
pin data input register (PDIN) 5-11
pin data output register (PDOUT) 5-13
pin data set register (PDSET) 5-15
pin direction register (PDIR) 5-8
pin function register (PFUNC) 5-6
pin interrupt clear register (PICLR) 5-25
pin interrupt enable register (PIEN) 5-19
pin interrupt polarity register (PIPOL) 5-21
pin interrupt status register (PISTAT) 5-23
status register (VPSTAT) 2-20
related documentation from Texas Instruments iii
reset operation 2-2
RESMPL 4-55
RESMPL bit
in VCACTL 3-53
in VCBCTL 3-68
REVISION bits 5-3
RGBX 4-55
RSTCH bit 4-55
in VCACTL 3-53
in VCBCTL 3-68
RSYNC 4-55
S
SCALE bit 4-55
in VCACTL 3-53
in VCBCTL 3-68
SERRA bit
in VPIE 2-21
in VPIS 2-24
SERRB bit
in VPIE 2-21
in VPIS 2-24
SFDA bit
in VPIE 2-21
in VPIS 2-24
SFDB bit
in VPIE 2-21
in VPIS 2-24
SFDE bit
in VCACTL 3-53
in VCBCTL 3-68
SOFT bit 5-4
software port reset 2-3
SSE bit 3-58
STC bit
in VPIE 2-21
in VPIS 2-24
STEN bit 3-72
T
TCKEN bit 3-72
throughput and latency 2-13
TICK bit
in VPIE 2-21
in VPIS 2-24
TICKCT bits 3-82
trademarks iv
TSI bit 2-17
TSI capture control register (TSICTL) 3-72
TSI capture mode 3-37
capture selection 3-40
capturing data 3-47
data capture 3-37
data capture notification 3-40
error detection 3-38
features 3-37
FIFO overrun 3-48
mode selection 3-2
reading from the FIFO 3-42
synchronizing the system clock 3-38
timestamp format (big endian) 3-42
timestamp format (little endian) 3-41
writing to the FIFO 3-41