Texas Instruments TMS320C64x DSP User Manual
Page 267

GPIO Registers
General Purpose I/O Operation
5-26
SPRU629
Table 5–13. Video Port Pin Interrupt Clear Register (PICLR) Field Descriptions
Bit
field
†
symval
†
Value
Description
31–23
Reserved
–
0
Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
22
PICLR22
Allows PISTAT22 bit to be cleared to a logic low.
NONE
0
No effect.
VCTL3CLR
1
Clears PISTAT22 (VCTL3) bit to 0.
21
PICLR21
Allows PISTAT21 bit to be cleared to a logic low.
NONE
0
No effect.
VCTL2CLR
1
Clears PISTAT21 (VCTL2) bit to 0.
20
PICLR20
Allows PISTAT20 bit to be cleared to a logic low.
NONE
0
No effect.
VCTL1CLR
1
Clears PISTAT20 (VCTL1) bit to 0.
19–0
PICLR[19–0]
Allows PISTAT[19–0] bit to be cleared to a logic low.
NONE
0
No effect.
VDATAnCLR
1
Clears PISTAT[n] (VDATA[n]) bit to 0.
† For CSL implementation, use the notation VP_PICLR_PICLRn_symval
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