Texas Instruments TMS320C64x DSP - Manual (Page 259)

GPIO Registers
General Purpose I/O Operation 5-18 SPRU629
Table 5–9. Video Port Pin Data Clear Register (PDCLR) Field Descriptions
Bit field † symval † Value Description
31–23 Reserved – 0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
22 PDCLR22 Allows PDOUT22 bit to be cleared to a logic low without
affecting other I/O pins controlled by the same port.
NONE 0 No effect.
VCTL3CLR 1 Clears PDOUT22 (VCTL3) bit to 0.
21 PDCLR21 Allows PDOUT21 bit to be cleared to a logic low without
affecting other I/O pins controlled by the same port.
NONE 0 No effect.
VCTL2CLR 1 Clears PDOUT21 (VCTL2) bit to 0.
20 PDCLR20 Allows PDOUT20 bit to be cleared to a logic low without
affecting other I/O pins controlled by the same port.
NONE 0 No effect.
VCTL1CLR 1 Clears PDOUT20 (VCTL1) bit to 0.
19–0 PDCLR[19–0] Allows PDOUT[19–0] bit to be cleared to a logic low without
affecting other I/O pins controlled by the same port.
NONE 0 No effect.
VDATAnCLR 1 Clears PDOUT[n] (VDATA[n]) bit to 0.
† For CSL implementation, use the notation VP_PDCLR_PDCLRn_symval