Texas Instruments TMS320C64x DSP - Manual (Page 206)

Video Display Registers
4-61 Video Display Port SPRU629
4.12.4 Video Display Horizontal Blanking Register (VDHBLNK)
The video display horizontal blanking register (VDHBLNK) controls the display
horizontal blanking. The VDHBLNK is shown in Figure 4–42 and described in
Table 4–9.
Every time the frame pixel counter (FPCOUNT) is equal to HBLNKSTART,
HBLNK is asserted. HBLNKSTART also determines where the EAV code is
inserted in the BT.656 and Y/C output.
Every time FPCOUNT = HBLNKSTOP, the HBLNK signal is deasserted (this
is shown in Figure 4–5, page 4-6). In BT.656 and Y/C modes, HBLNKSTOP
determines the SAV code insertion point and HBLNK deassertion point. The
HBLNK inactive edge may optionally be delayed by 4 pixel clocks using the
HBDLA bit.
Figure 4–42. Video Display Horizontal Blanking Register (VDHBLNK)
31 28 27 16
Reserved HBLNKSTOP
R-0 R/W-0
15 14 12 11 0
HBDLA Reserved HBLNKSTART
R/W-0 R-0 R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset