Texas Instruments TMS320C64x DSP - Manual (Page 292)

Example 2: Noncontinuous Frame Display for 525/60 Format
Video Port Configuration Examples A-16 SPRU629
/* set vertical sync end for field2 (VCTL2S) */
VP_RSETH(vpDisplayHandle , VDVSYNE2,
VP_VDVSYNE2_RMK(VD_VSYNC_YSTOP2, VD_VSYNC_XSTOP2));
/* Let clipping values to be their defaults (VD_CLIP) */
/* No need to set DEF_VAL and VD_RELOAD in this example */
/* set event register */
VP_RSETH(vpDisplayHandle , VDDISPEVT,
VP_VDDISPEVT_RMK(VD_DISPEVT2, VD_DISPEVT1));
/* Vertical interrupts are not used in this example (VD_VINT) */
/* set threshold value for DMA events */
VP_RSETH(vpDisplayHandle, VDTHRLD,
VP_VDTHRLD_RMK(VD_VDTHRLD2,
VP_VDTHRLD_INCPIX_DEFAULT, VD_VDTHRLD1));
/* ––––––––––––––––––––––––––––––– */
/* Set display control reg(VD_CTL) */
/* ––––––––––––––––––––––––––––––– */
/* set display mode(DMODE) to 8–bit BT.656 */
VP_FSETH(vpDisplayHandle , VDCTL, DMODE, VP_VDCTL_DMODE_BT656B);
/* set non–continuous frame display */
VP_FSETH(vpDisplayHandle , VDCTL, CON, VP_VDCTL_CON_DISABLE);
VP_FSETH(vpDisplayHandle , VDCTL, FRAME, VP_VDCTL_FRAME_FRMDIS);
VP_FSETH(vpDisplayHandle , VDCTL, DF2, VP_VDCTL_DF2_NONE);
VP_FSETH(vpDisplayHandle , VDCTL, DF1, VP_VDCTL_DF1_NONE);
/* let control outputs(VCTL1S, VCTL2S, VCTL3S, HXS, VXS, FXS) */
/* be their defaults i.e. VCTLxS are output control signals */
/* no scaling and no resampling in this example */
/* no need to bother about 10–bit unpacking mode(DPK bit) */
/* in this 8–bit example */
/* Set up Y, Cb and Cr EDMA channels */
setupVPDispEDMA(portNumber);
/* Enable video port interrupts */
IRQ_enable(vpDisplayHandle –>eventId);
/* clear VPHLT in VP_CTL to make video port function */
VP_FSETH(vpDisplayHandle , VPCTL, VPHLT, VP_VPCTL_VPHLT_CLEAR);