Texas Instruments TMS320C64x DSP - Manual (Page 189)

Display T
iming
Examples
4-44
V
ideo Display Port
SPRU629
Figure 4–37. Y/C Progressive Display Horizontal Timing Example
‡
ЙЙ
ЙЙ
ЙЙ
VCLKIN
FPCOUNT
IPCOUNT
VCTL1 (HBLNK)† §
VCTL1 (HSYNC)† §
VCLKOUT
VDOUT[9–0] §
VDOUT[19–0] §
FLCOUNT n – 1 n + 1 n
EAV Blanking Data SAV EAV
Blanking Active Video
Display Image
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1349 1350 1429 1430 1644 1645 1646 1647 1648 1649
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FRMWIDTH = 1650 IMGHOFF1 = 8 HSYNCSTART = 1350
HBLNKSTART = 1280 IMGHSIZE1 = 1264 HSYNCSTOP = 1430
HBLNKSTOP = 1646 IMGHOFF2 = n/a
IMGHSIZE2 = n/a
† Assumes VCT1P bit in VPCTL is set to 1 (active-low output). HSYNC output when VCTL1S bit in VDCTL is set to 00,
HBLNK output when VCTL1S bit is set 01.
‡ HBLNK operation when HBDLA bit in VDHBLNK is set to 1.
§ Diagram assumes a two VCLK pipeline delay between internal counters and output signals.