Texas Instruments TMS320C64x DSP - Manual (Page 238)

Video Display Registers
4-93 Video Display Port SPRU629
Table 4–33. Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2)
Field Descriptions
Description
Bit field † symval † Value BT.656 and Y/C Mode Raw Data Mode
31–28 Reserved – 0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
27–16 VBITCLR2 OF(value) 0–FFFh Specifies the first line with an EAV of
V = 0 indicating the start of field 2
active display. Not used.
15–12 Reserved – 0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
11–0 VBITSET2 OF(value) 0–FFFh Specifies the first line with an EAV of
V = 1 indicating the start of field 2
vertical blanking. Not used.
† For CSL implementation, use the notation VP_VDVBIT2_field_symval