Texas Instruments TMS320C64x DSP User Manual
Page 128
Video Capture Registers
Video Capture Port
3-66
SPRU629
Figure 3–36. Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD)
31
26
25
16
Reserved
VCTHRLD2
R-0
R/W-0
15
10
9
0
Reserved
VCTHRLD1
R-0
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 3–21. Video Capture Channel x Threshold Register (VCxTHRLD) Field Descriptions
Description
Bit
field
†
symval
†
Value
BT.656 or Y/C Mode
Raw Data Mode
TSI Mode
31–26
Reserved
–
0
Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
25–16
VCTHRLD2
OF(value)
0–3FFh
Number of field 2
doublewords
required to generate
DMA events.
Not used.
Not used.
15–10
Reserved
–
0
Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
9–0
VCTHRLD1
OF(value)
0–3FFh
Number of field 1
doublewords
required to generate
DMA events.
Number of raw
data doublewords
required to
generate a DMA
event.
Number of
doublewords
required to
generate a DMA
event.
† For CSL implementation, use the notation VP_VCxTHRLD_VCTHRLDn_symval