Texas Instruments TMS320C64x DSP - Manual (Page 212)

Video Display Registers
4-67 Video Display Port SPRU629
4.12.8 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)
The video display field 2 vertical blanking end register (VDVBLKE2) controls
the end of vertical blanking in field 2. The VDVBLKE2 is shown in Figure 4–46
and described in Table 4–13.
In raw data mode, VBLNK is deasserted whenever the frame line counter
(FLCOUNT) is equal to VBLNKYSTOP2 and the frame pixel counter (FPCOUNT)
is equal to VBLNKXSTOP2 (this is shown in Figure 4–6, page 4-7).
In BT.656 and Y/C mode, VBLNK is deasserted whenever
FLCOUNT = VBLNKYSTOP2 and FPCOUNT = VBLNKXSTOP2. This
VBLNK output control is completely independent of the timing control codes.
The V bit in the EAV/SAV codes for field 2 is controlled by the VDVBIT2 register.
Figure 4–46. Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)
31 28 27 16
Reserved VBLNKYSTOP2
R-0 R/W-0
15 12 11 0
Reserved VBLNKXSTOP2
R-0 R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset