Texas Instruments TMS320C64x DSP - Manual (Page 131)

Video Capture Registers
3-69 Video Capture Port SPRU629
Table 3–23. Video Capture Channel B Control Register (VCBCTL)
Field Descriptions (Continued)
Description
Bit TSI Mode Raw Data Mode BT.656 or Y/C Mode Value symval † field †
30 BLKCAP Block capture events bit. BLKCAP functions as a capture FIFO
reset without affecting the current programmable register values.
The F1C, F2C, and FRMC status bits, in VCBSTAT, are not
updated. Field or frame complete interrupts and vertical interrupts
are also not generated.
Clearing BLKCAP does not enable DMA events during the field
where the bit is cleared. Whenever BLKCAP is set and then
cleared, the software needs to clear the field and frame status
bits (F1C, F2C, and FRMC) as part of the BLKCAP clear
operation.
CLEAR 0 Enables DMA events in the video frame that follows the video
frame where the bit is cleared. (The capture logic must sync to
the start of the next frame after BLKCAP is cleared.)
BLOCK 1 Blocks DMA events and flushes the capture channel FIFOs.
29–21 Reserved – 0 Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
20 FINV Detected field invert bit.
FIELD1 0 Detected 0 is field 1. Not used. Not used.
FIELD2 1 Detected 0 is field 2. Not used. Not used.
19–18 Reserved – 0 Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
17 VRST VCOUNT reset method bit.
V1EAV 0 Start of vertical blank
(1
st V = 1 EAV or
VCTL2 active edge)
Not used. Not used.
V0EAV 1 End of vertical blank
(1
st V = 0 EAV or
VCTL2 inactive edge)
Not used. Not used.
† For CSL implementation, use the notation VP_VCBCTL_field_symval
‡ For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.