43 port x mac interrupt mask register (mac_imr_x), Port x mac interrupt mask register (mac_imr_x), Port x mac interrupt mask – SMSC LAN9311i User Manual

Page 366: Register (mac_imr_x), Section 14.5.2.43, Datasheet

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

Revision 1.4 (08-19-08)

366

SMSC LAN9311/LAN9311i

DATASHEET

14.5.2.43

Port x MAC Interrupt Mask Register (MAC_IMR_x)

This register contains the Port x interrupt mask. Port x related interrupts in the

Port x MAC Interrupt

Pending Register (MAC_IPR_x)

may be masked via this register. An interrupt is masked by setting the

corresponding bit of this register. Clearing a bit will unmask the interrupt. Refer to

Chapter 5, "System

Interrupts," on page 49

for more information.

Note:

There are no possible Port x interrupt conditions available. This register exists for future use,
and should be configured as indicated for future compatibility.

Port0: 0480h

Size:

32 bits

Port1: 0880h
Port2: 0C80h

BITS

DESCRIPTION

TYPE

DEFAULT

31:8

RESERVED

7:0

RESERVED

Note:

These bits must be written as 11h

R/W

11h

This manual is related to the following products:

LAN9311