SMSC LAN9311i - Manual (Page 259)

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i 259 Revision 1.4 (08-19-08)
DATASHEET
Note 14.42 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on
a DWORD boundary. When accessed serially (through the MII management protocol), the
register is 16-bits wide.
Note 14.43 The default value of this field is the result of the Auto-Negotiation process if the Auto-
N e g o t i a t i o n ( V P H Y _ A N ) b i t o f t h e V i r t u a l P H Y B a s i c C o n t r o l R e g i s t e r
(VPHY_BASIC_CTRL) is set. Otherwise, this field reflects the Speed Select LSB
(VPHY_SPEED_SEL_LSB) and Duplex Mode (VPHY_DUPLEX) bit settings of the
VPHY_BASIC_CTRL register. Refer to Section 7.3.1, "Virtual PHY Auto-Negotiation," on
page 96 for information on the Auto-Negotiation determination process of the Virtual PHY.
Note 14.44 Register bits designated as NASR are reset when the Virtual PHY Reset is generated via
the
Reset Control Register (RESET_CTL) or Power Management Control Register
(PMT_CTRL) . The NASR designation is only applicable when the Reset (VPHY_RST) bit
of the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) is set.
Note 14.45 The default value of this field is determined via the SQE_test_disable_strap_mii
configuration strap. Refer to
Section 4.2.4, "Configuration Straps," on page 40 for
additional information.