SMSC LAN9311i - Manual (Page 315)

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i 315 Revision 1.4 (08-19-08)
DATASHEET
0C42h-0C50h RESERVED Reserved for Future Use
0C51h MAC_TX_DEFER_CNT_2 Port 2 MAC Transmit Deferred Count Register,
Section 14.5.2.25
0C52h MAC_TX_PAUSE_CNT_2 Port 2 MAC Transmit Pause Count Register, Section 14.5.2.26
0C53h MAC_TX_PKTOK_CNT_2 Port 2 MAC Transmit OK Count Register, Section 14.5.2.27
0C54h MAC_RX_64_CNT_2 Port 2 MAC Transmit 64 Byte Count Register, Section 14.5.2.28
0C55h MAC_TX_65_TO_127_CNT_2 Port 2 MAC Transmit 65 to 127 Byte Count Register,
Section 14.5.2.29
0C56h MAC_TX_128_TO_255_CNT_2 Port 2 MAC Transmit 128 to 255 Byte Count Register,
Section 14.5.2.30
0C57h MAC_TX_256_TO_511_CNT_2 Port 2 MAC Transmit 256 to 511 Byte Count Register,
Section 14.5.2.31
0C58h MAC_TX_512_TO_1023_CNT_2 Port 2 MAC Transmit 512 to 1023 Byte Count Register,
Section 14.5.2.32
0C59h MAC_TX_1024_TO_MAX_CNT_2 Port 2 MAC Transmit 1024 to Max Byte Count Register,
Section 14.5.2.33
0C5Ah MAC_TX_UNDSZE_CNT_2 Port 2 MAC Transmit Undersize Count Register,
Section 14.5.2.34
0C5Bh RESERVED Reserved for Future Use
0C5Ch MAC_TX_PKTLEN_CNT_2 Port 2 MAC Transmit Packet Length Count Register,
Section 14.5.2.35
0C5Dh MAC_TX_BRDCST_CNT_2 Port 2 MAC Transmit Broadcast Count Register,
Section 14.5.2.36
0C5Eh MAC_TX_MULCST_CNT_2 Port 2 MAC Transmit Multicast Count Register,
Section 14.5.2.37
0C5Fh MAC_TX_LATECOL_2 Port 2 MAC Transmit Late Collision Count Register,
Section 14.5.2.38
0C60h MAC_TX_EXCOL_CNT_2 Port 2 MAC Transmit Excessive Collision Count Register,
Section 14.5.2.39
0C61h MAC_TX_SNGLECOL_CNT_2 Port 2 MAC Transmit Single Collision Count Register,
Section 14.5.2.40
0C62h MAC_TX_MULTICOL_CNT_2 Port 2 MAC Transmit Multiple Collision Count Register,
Section 14.5.2.41
0C63h MAC_TX_TOTALCOL_CNT_2 Port 2 MAC Transmit Total Collision Count Register,
Section 14.5.2.42
0C64-0C7Fh RESERVED Reserved for Future Use
0C80h MAC_IMR_2 Port 2 MAC Interrupt Mask Register, Section 14.5.2.43
0C81h MAC_IPR_2 Port 2 MAC Interrupt Pending Register, Section 14.5.2.44
0C82 h -17FF h RESERVED Reserved for Future Use
Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued)
REGISTER # SYMBOL REGISTER NAME