SMSC LAN9311i - Manual (Page 21)

T
w
o Port 10/100
M
ana
ged Ether
net
Switc
h
w
ith
16-Bi
t N
on-PCI CPU
Interface
Dat
ashe
e
t
Revision 1.4 (0
8-19-
08)
21
SMSC LAN931
1/LAN931
1
i
DA
T
ASHEET
2.2 Block Diagram
Figure 2.1 Internal LAN9311/LAN9311i Block Diagram
To optional
EEPROM
EEPROM Controller
I 2 C (master)
Microwire (master)
EEPROM Loader
Register
Access
MUX
System
Registers
(CSRs)
I 2 C/Microwire
MII
IEEE 1588
Time Stamp
Registers
Virtual PHY
10/100
PHY
Registers
10/100
PHY
Registers
Switch
Registers
(CSRs)
IEEE 1588
Time Stamp
IEEE 1588
Time Stamp
Switch Fabric
GPIO/LED
Controller
Dy
nam
ic
QoS
4 Qu
eu
es
Dy
nam
ic
Qo
S
4
Q
ueu
es
Dy
nam
ic
QoS
4 Qu
eu
es
Switch Engine
Buffer Manager
Search
Engine
Frame
Buffers
IEEE 1588
Time Stamp
Clock/Events
MII
MDIO
MII
MDIO
To optional GPIOs/LEDs
To Ethernet
To Ethernet
LAN9311/LAN9311i
Host Bus Interface
TX/RX FIFOs
Host MAC
To 16-bit
Host Bus
System
Interrupt
Controller
IRQ
GP Timer
Free-Run
Clk
System
Clocks/
Reset/PME
Controller
External
25MHz Crystal
MDIO MDIO
MDIO
Po
rt 0
10/100
MAC
Po
rt 2
10/100
MAC
Po
rt 1
10/100
MAC