Section 14.5.2.25, Through, Datasheet – SMSC LAN9311i User Manual

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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

Revision 1.4 (08-19-08)

348

SMSC LAN9311/LAN9311i

DATASHEET

14.5.2.25

Port x MAC Transmit Deferred Count Register (MAC_TX_DEFER_CNT_x)

This register provides a counter deferred packets. The counter is cleared upon being read.

Port0: 0451h

Size:

32 bits

Port1: 0851h
Port2: 0C51h

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

TX Deferred
Count of packets that were available for transmission but were deferred on
the first transmit attempt due to network traffic (either on receive or prior
transmission). This counter is not incremented on collisions. This counter is
incremented only in half-duplex operation.

Note:

This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.

00000000h

This manual is related to the following products:

LAN9311