6 write access, 7 read access, 8 µcontroller access errors – BECKHOFF ET1100 User Manual
Page 95: 9 eeprom_loaded, Write access, Read access, Μcontroller access errors, Eeprom_loaded

PDI description
Slave Controller
– ET1100 Hardware Description
III-81
6.5.6
Write access
A write access starts with a Transfer Start (TS). Chip Select can be either together with TS or one
clock cycle later (does not need to be configured). The CPU_CLK_IN edge at which CS is sampled
can be configured. ADR, BHE and R/nW are valid together with TS. It is configurable if write DATA is
also valid with CS or one cycle later. Once the EtherCAT device has finished the access, Transfer
Acknowledge is asserted for one clock cycle. It may either be generated with the rising or falling edge
of CPU_CLK_IN.
6.5.7
Read access
A read access starts with a Transfer Start (TS). Chip Select can be either together with TS or one
clock cycle later (does not need to be configured). The CPU_CLK_IN edge at which CS is sampled
can be configured. ADR, BHE and R/nW are valid together with TS. Once the EtherCAT device has
finished the access, Transfer Acknowledge is asserted for one clock cycle together with the read
DATA. TA may either be generated with the rising or falling edge of CPU_CLK_IN.
Some µControllers expect a read access always to be a 16 bit read access, regardless of the Byte
Select signals. For this reason, it is configurable that the Byte Select signals are ignored and a read
access is always a 16 bit access.
6.5.8
µController access errors
One reason for µController access errors is detected by the synchronous µController interface:
Read or Write access to the 16 bit interface with A[0]=1 and BHE(act. low)=1, i.e. an access to an
odd address without Byte High Enable.
Such a wrong µController access will have these consequences:
The PDI error counter 0x030D will be incremented.
No access will be performed internally.
6.5.9
EEPROM_LOADED
The EEPROM_LOADED signal indicates that the µController Interface is operational. Attach a pull-
down resistor for proper function, since the PDI pin will not be driven until the EEPROM is loaded.
EEPROM_LOADED is synchronous to CPU_CLK_IN, it will not go high if CPU_CLK_IN is not
toggling.