BECKHOFF ET1100 - Manual (Page 74)

PDI description
III-60 Slave Controller – ET1100 Hardware Description
6.3.12 Timing specifications
Table 63: SPI timing characteristics ET1100
Parameter Min Max Comment
t
CLK
50 ns SPI_CLK frequency (f
CLK
≤ 20 MHz)
t
SEL_to_CLK
6 ns First SPI_CLK cycle after SPI_SEL
asserted
t
CLK_to_SEL
a) 5 ns
b) t
CLK
/2+5 ns
Deassertion of SPI_SEL after last
SPI_CLK cycle
a) SPI mode 0/2, SPI mode 1/3 with
normal data out sample
b) SPI mode 1/3 with late data out sample
t
read
240 ns Only for read access between
address/command and first data byte.
Can be ignored if Wait State Bytes are
used.
t
SEL_to_DO_valid
15 ns Status/Interrupt Byte 0 bit 7 valid after
SPI_SEL asserted
t
SEL_to_DO_invalid
0 ns Status/Interrupt Byte 0 bit 7 invalid after
SPI_SEL de-asserted
t
STATUS_valid
12 ns Time until status of last access is valid.
Can be ignored if status is not used.
t
access_delay
a) 15 ns
b) 240 ns Delay between SPI accesses
a) typical
b) If last access was shorter than 2 bytes,
otherwise Interrupt Request Register
value I0_[7:0] will not be valid.
t
DI_setup
9 ns SPI_DI valid before SPI_CLK edge
t
DI_hold
3 ns SPI_DI valid after SPI_CLK edge
t
CLK_to_DO_valid
15 ns SPI_DO valid after SPI_CLK edge
t
CLK_to_DO_invalid
0 ns SPI_DO invalid after SPI_CLK edge
t
EEPROM_LOADED_to_acce
ss
0 ns Time between EEPROM_LOADED and
first access
t
IRQ_delay
160 ns Internal delay between AL event and
SPI_IRQ output to enable correct reading
of the interrupt registers.