BECKHOFF ET1100 - Manual (Page 35)

Pin Description
Slave Controller – ET1100 Hardware Description III-21
3.3 General ET1100 Pins
Table 26: General pins
Pin
Pin Signal Configuration
Signal Internal
PU/PD
Name Dir. Signal Dir.
G12 OSC_IN I OSC_IN I
F12 OSC_OUT O OSC_OUT O
H12 RESET BD RESET BD 3.3 k Ω PU
C4 RBIAS RBIAS
H3 TESTMODE I TESTMODE I WPD
OSC_IN
Connection to external crystal or oscillator input (25 MHz). An oscillator as the clock source for both
ET1100 and PHYs is mandatory if MII ports are used and CLK25OUT1/2 cannot be used as the clock
source for the PHYs. The 25 MHz clock source should have an initial accuracy of 25ppm or better.
OSC_OUT
Connection to external crystal. Should be left open if an oscillator is connected to OSC_IN.
RESET
The open collector RESET input/output (active low) signals the reset state of ET1100. The reset state
is entered at power-on, if the power supply is to low, or if a reset was initiated using the reset register
0x0040. ET1100 also enters reset state if RESET pin is held low by external devices
RBIAS
Bias resistor for LVDS TX current adjustment, should be 11 k
Ω connected to GND.
TESTMODE
Reserved for testing, should be connected to GND.
3.4 SII EEPROM Interface Pins
Table 27: SII EEPROM pins
Pin
Pin Signal
Configuration
Signal Internal
PU/PD
Name Dir. Signal Dir.
G11 EEPROM_CLK BD EEPROM_CLK BD 3.3 k Ω PU
F11 EEPROM_DATA BD EEPROM_DATA BD 3.3 k Ω PU
EEPROM_CLK
EEPROM I²C clock signal (open collector output).
EEPROM_DATA
EEPROM I²C data signal (open collector output).