BECKHOFF ET1100 - Manual (Page 81)

PDI description
Slave Controller – ET1100 Hardware Description III-67
6.4.3 µController access
The 8 bit µController interface reads or writes 8 bit per access, the 16 bit µController interface
supports both 8 bit and 16 bit read/write accesses. For the 16 bit µController interface, the least
significant address bit together with Byte High Enable (BHE) are used to distinguish between 8 bit low
byte access, 8 bit high byte access and 16 bit access.
EtherCAT devices use Little Endian byte ordering.
Table 66: 8 bit µController interface access types
ADR[0] Access DATA[7:0]
0 8 bit access to ADR[15:0] (low byte, even address) low byte
1 8 bit access to ADR[15:0] (high byte, odd address) high byte
Table 67: 16 bit µController interface access types
ADR[0]
BHE
(act. low)
Access
DATA[15:8] DATA[7:0]
0 0 16 bit access to ADR[15:0] and
ADR[15:0]+1 (low and high byte) high byte low byte
0 1 8 bit access to ADR[15:0]
(low byte, even address) (RD only: copy
of low byte) low byte
1 0 8 bit access to ADR[15:0]
(high byte, odd address) high byte (RD only: copy of
high byte)
1 1 invalid access - -
6.4.4 Write access
A write access starts with assertion of Chip Select (CS), if it is not permanently asserted. Address,
Byte High Enable and Write Data are asserted with the falling edge of WR (active low). Once the
µController interface is not BUSY, a rising edge on WR completes the µController access. A write
access can be terminated either by deassertion of WR (while CS remains asserted), or by deassertion
or CS (while WR remains asserted), or even by deassertion of WR and CS simultaneously. Shortly
after the rising edge of WR, the access can be finished by de-asserting ADR, BHE and DATA. The
µController interface indicates its internal operation with the BUSY signal. Since the BUSY signal is
only driven while CS is asserted, the BUSY driver will be released after CS deassertion.
Internally, the write access is performed after the rising edge of WR, this allows for fast write
accesses. Nevertheless, an access following immediately will be delayed by the preceding write
access (BUSY is active for a longer time).
6.4.5 Read access
A read access starts with assertion of Chip Select (CS), if it is not permanently asserted. Address and
BHE have to be valid before the falling edge of RD, which signals the start of the access. The
µController interface will show its BUSY state afterwards
– if it is not already busy executing a
preceding write access – and release BUSY when the read data are valid. The read data will remain
valid until either ADR, BHE, RD or CS change. The data bus will be driven while CS and RD are
asserted. BUSY will be driven while CS is asserted.
With read busy delay configuration, BUSY deassertion for read accesses can be additionally delayed
for 20 ns, so external DATA setup requirements in respect to BUSY can be met.