BECKHOFF ET1100 - Manual (Page 84)

PDI description
III-70 Slave Controller – ET1100 Hardware Description
6.4.10 Timing Specification
Table 68: µController timing characteristics ET1100
Parameter Min Max Comment
t
CS_to_BUSY
15 ns BUSY driven and valid after CS assertion
t
ADR_BHE_setup
-2 ns ADR and BHE valid before RD assertion
t
RD_to_DATA_driven
0 ns DATA bus driven after RD assertion
t
RD_to_BUSY
0 ns 15 ns BUSY asserted after RD assertion
t
read
External read time (RD assertion to BUSY
deassertion) with normal read busy output
(0x0152[0]). Additional 20 ns with delayed
read busy output.
a) t
read_int
+ t
prec_write
+t
Coll
-t
WR_to_RD
a) with preceding write access and
t
WR_to_RD
< t
prec_write
+ t
Coll
b) t
read_int
b) without preceding write access or
t
WR_to_RD
≥ t
prec_write
+ t
Coll
c) 435 ns c) 8 bit access, absolute worst case with
preceding 8 bit write access (t
WR_to_RD
=min
,
t
prec_write
=max, t
Coll
=max)
d) 575 ns d) 16 bit access, absolute worst case with
preceding 16 bit write access (t
WR_to_RD
=min
,
t
prec_write
=max, t
Coll
=0)
t
read_int
a) 235 ns
b) 315 ns Internal read time
a) 8 bit access
b) 16 bit access
t
prec_write
a) 180 ns
b) 260 ns Time for preceding write access
a) 8 bit access
b) 16 bit access
t
BUSY_to_DATA_valid
a) 5 ns
b) -15 ns DATA bus valid after device BUSY is de-
asserted
a) normal read busy output
b) delayed read busy output
t
ADR_BHE_to_DATA_invalid
0 ns DATA invalid after ADR or BHE change
t
CS_RD_to_DATA_release
0 ns DATA bus released after CS deassertion or
RD deassertion
t
CS_to_BUSY_release
0 ns 15 ns BUSY released after CS deassertion
t
CS_delay
0 ns Delay between CS deassertion an assertion
t
RD_delay
10 ns Delay between RD deassertion and
assertion
t
ADR_BHE_DATA_setup
10 ns ADR, BHE and Write DATA valid before WR
deassertion
t
ADR_BHE_DATA_hold
3 ns ADR, BHE and Write DATA valid after WR
deassertion
t
WR_active
10 ns WR assertion time
t
BUSY_to_WR_CS
0 ns WR or CS deassertion after BUSY
deassertion
t
WR_to_BUSY
15 ns BUSY assertion after WR deassertion
t
write
0 ns External write time (WR assertion to BUSY
deassertion)