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TABLES
III-X
Slave Controller
– ET1100 Hardware Description
Table 1: ET1100 Main Features .............................................................................................................. 1
Table 2: Frame Processing Order ........................................................................................................... 2
Table 3: Revision/Build History................................................................................................................ 3
Table 4: ET1100 Feature Details ............................................................................................................ 4
Table 5: Legend ....................................................................................................................................... 6
Table 6: Register Overview Legend ........................................................................................................ 7
Table 7: Register Overview ..................................................................................................................... 7
Table 8: Pin Overview ........................................................................................................................... 10
Table 9: Signal Overview ....................................................................................................................... 12
Table 10: PDI signal overview ............................................................................................................... 13
Table 11: Port Mode .............................................................................................................................. 14
Table 12: Port Configuration .................................................................................................................. 14
Table 13: Configurations with 2 ports (P_MODE[1:0]=00) .................................................................... 15
Table 14: Configurations with 3 ports (ports 0,1, and 2; P_MODE[1:0]=01) ......................................... 15
Table 15: Configurations with 3 ports (ports 0, 1, and 3; P_MODE[1:0]=10) ........................................ 15
Table 16: Configurations with 4 ports (P_MODE[1:0]=01) .................................................................... 16
Table 17: CPU_CLK Mode .................................................................................................................... 17
Table 18: TX Shift .................................................................................................................................. 17
Table 19: CLK25OUT2 Enable .............................................................................................................. 17
Table 20: Transparent Mode Enable ..................................................................................................... 18
Table 21: Digital Control/Status Move ................................................................................................... 19
Table 22: PHY Address Offset .............................................................................................................. 19
Table 23: Link Polarity ........................................................................................................................... 19
Table 24: SII EEPROM_SIZE ................................................................................................................ 20
Table 25: Reserved ............................................................................................................................... 20
Table 26: General pins .......................................................................................................................... 21
Table 27: SII EEPROM pins .................................................................................................................. 21
Table 28: MII Management pins ............................................................................................................ 22
Table 29: DC SYNC/LATCH pins .......................................................................................................... 22
Table 30: LED pins ................................................................................................................................ 23
Table 31: Combinations of physical ports and PDI ............................................................................... 24
Table 32: CLK25OUT1/2 signal output ................................................................................................. 25
Table 33: Physical Port 0 ....................................................................................................................... 27
Table 34: Physical Port 1 ....................................................................................................................... 28
Table 35: Physical Port 2/PDI byte 4 ..................................................................................................... 29
Table 36: Physical Port 2 ....................................................................................................................... 29
Table 37: Physical Port 3 / PDI.............................................................................................................. 30
Table 38: PDI pins ................................................................................................................................. 31
Table 39: Mapping of Digital I/O Interface (1) ....................................................................................... 33
Table 40: Mapping of Digital I/O Interface (2) ....................................................................................... 34
Table 41: Mapping of Digital I/O Interface (3) ....................................................................................... 35
Table 42: Mapping of synchronous µC Interface to Port ....................................................................... 37
Table 43: Mapping of SPI Interface to Port (2) ...................................................................................... 39
Table 44: Power supply options (all voltages nominal) ......................................................................... 40
Table 45: I/O power supply ................................................................................................................... 41
Table 46: Core Power Supply................................................................................................................ 42
Table 47: PLL Power Supply ................................................................................................................. 42
Table 48: Reserved Pins ....................................................................................................................... 42
Table 49: MII Interface signals .............................................................................................................. 44
Table 50: TX Shift Timing characteristics .............................................................................................. 45
Table 51: MII timing characteristics ....................................................................................................... 46
Table 52: EBUS Interface signals ......................................................................................................... 47
Table 53: Available PDIs for ET1100 .................................................................................................... 48
Table 54: ET1100 Digital I/O signals ..................................................................................................... 49
Table 55: Output Enable/Output Configuration combinations ............................................................... 52
Table 56: Digital I/O timing characteristics ET1100 .............................................................................. 53
Table 57: SPI signals ............................................................................................................................. 55
Table 58: SPI commands CMD0 and CMD1 ......................................................................................... 56
Table 59: Address modes without (Read access without Wait state byte) ........................................... 56
Table 60: Address modes for Read access with Wait state byte .......................................................... 57
