BECKHOFF ET1100 - Manual (Page 73)

PDI description
Slave Controller – ET1100 Hardware Description III-59
6.3.9 SPI access errors and SPI status flag
The following reasons for SPI access errors are detected by the SPI slave:

The number of clock cycles recognized while SPI_SEL is asserted is not a multiple of 8
(incomplete bytes were transferred).

For a read access, a clock cycle occurred while the slave was busy fetching the first data byte.

For a read access, the data phase was not terminated by setting SPI_DI to high for the last byte.

For a read access, additional bytes were read after termination of the access.
A wrong SPI access will have these consequences:

Registers will not accept write data (nevertheless, RAM will be written).

Special functions are not executed (e.g., SyncManager buffer switching).

The PDI error counter 0x030D will be incremented.

A status flag will indicate the error until the next access (not for SPI mode 0/2 with normal data out
sample)
A status flag, which indicates if the last access had an error, is available in any mode except for SPI
mode 0/2 with normal data out sample. The status flag is presented on SPI_DO (MISO) after the slave
is selected (SPI_SEL) and until the first clock cycle occurs. So the status can be read either between
two accesses by assertion of SPI_SEL without clocking, or at the beginning of an access just before
the first clock cycle. The status flag will be high for a good access, and low for a wrong access.
6.3.10 EEPROM_LOADED
The EEPROM_LOADED signal indicates that the SPI Interface is operational. Attach a pull-down
resistor for proper function, since the PDI pin will not be driven until the EEPROM is loaded.
6.3.11 2 Byte and 4 Byte SPI Masters
Some SPI masters do not allow an arbitrary number of bytes per access, the number of bytes per
access must be a multiple of 2 or 4 (maybe even more). The SPI slave interface supports such
masters. The length of the data phase is in control of the master and can be set to the appropriate
length, the length of the address phase has to be extended. The address phase of a read access can
be set to a multiple of 2/4 by using the 3 byte address mode and a wait state byte. The address phase
of a write access can be enhanced to 4 bytes using 3 byte address mode and an additional address
extension byte (byte 2) according to Table 62.
Table 62: Write access for 2 and 4 Byte SPI Masters
Byte 2 Byte SPI master 4 Byte SPI master
0 A[12:5] address bits [12:5] A[12:5] address bits [12:5]
1 A[4:0] address bits [4:0]
CMD0[2:0] write command: 100b
A[4:0] address bits [4:0]
CMD0[2:0] 3 byte addressing: 110b
2 D0[7:0] data byte 0 A[15:13] address bits [15:13]
CMD1[2:0] 3 byte addressing: 110b
res[1:0]
two reserved bits, set to 00b
3 D1[7:0] data byte 1 A[15:13] address bits [15:13]
CMD2[2:0] write command: 100b
res[1:0]
two reserved bits, set to 00b
4 D2[7:0] data byte 2 D0[7:0] data byte 0
5 D3[7:0] data byte 3 D1[7:0] data byte 1
6 D4[7:0] data byte 4 D2[7:0] data byte 2
7 D5[7:0] data byte 5 D3[7:0] data byte 3
NOTE: The address phase of a write access can be further extended by an arbitrary number of address extension
bytes containing 110b as the command. The address phase of a read access can also be enhanced with
additional address extension bytes (the read wait state has to be maintained anyway). The address portion of the
last address extension byte is used for the access.