BECKHOFF ET1100 - Manual (Page 40)

Pin Description
III-26 Slave Controller – ET1100 Hardware Description
3.8.3 EBUS Interface
The EBUS ports of the ET1100 are open failsafe, i.e., the ET1100 detects if an EBUS port is
unconnected and closes the port internally (no physical link).
EBUS(x)-RX+/EBUS(x)-RX-
EBUS LVDS receive signals. EBUS_RX+ pins incorporate a pull-down resistor R
LI+
and EBUS_RX-
pins incorporate a pull-up resistor R
LI-
, even if the pins are not configured for EBUS.
EBUS(x)-TX+/EBUS(x)-TX-
EBUS LVDS transmit signals.
3.8.4 PDI Pins
PDI[x]
The function of PDI[x] signals depends on the configuration stored in the device SII EEPROM. PDI
signals are not driven (high impedance) until the EEPROM is loaded. This has to be taken into
account especially for Digital Outputs.
PDI signals are not driven (high impedance) if no PDI is configured (PDI Control register
0x0140=0x00).
CPU_CLK
The ET1100 can provide a clock signal for µControllers on pin PDI[7]/CPU_CLK. The CPU_CLK
output setting is controlled by the CLK_MODE configuration pin. If CPU_CLK is enabled, PDI[7] is not
available for the PDI, i.e., ADR[15] cannot be used by µController PDIs (ADR[15] is treated to be 0
internally), and I/O[7] is not available for Digital I/O PDIs.
CPU_CLK provides a clock signal – if configured – during external or ECAT reset, clock output is only
turned off during power-on reset.