BECKHOFF ET1100 - Manual (Page 31)

Pin Description
Slave Controller – ET1100 Hardware Description III-17
3.2.3 CPU_CLK MODE
CLK_MODE is used to provide a clock signal to an external microcontroller. If CLK_MODE is not 00,
CPU_CLK is available on PDI[7], thus this pin is not available for PDI signals anymore. For µController
PDIs, PDI[7] is ADR[15], which is treated to be 0 if CPU_CLK is selected. The CPU_CLK MODE is
shown in Table 17.
Table 17: CPU_CLK Mode
Description Config signal Pin name Register Values
CPU_CLK_MODE
CLK_MODE[0]
PERR(0)/
TRANS(0)/
CLK_MODE[0]
0x0E00[6]
00 = off, PDI[7]/CPU_CLK available for PDI
01 = 25 MHz clock output at PDI[7]/CPU_CLK
10 = 20 MHz clock output at PDI[7]/CPU_CLK
11 = 10 MHz clock output at PDI[7]/CPU_CLK
CLK_MODE[1]
PERR(1)/
TRANS(1)/
CLK_MODE(1)
0x0E00[7]
3.2.4 TX Shift
Phase shift (0/10/20/30ns) of MII TX signals (TX_ENA, TX_D[3:0]) can be attained via the C25_SHI[x]
signals. TX-Shift is explained in Table 18. It is recommended to support all C25_SHI[1:0]
configurations by hardware options to enable later adjustments.
Table 18: TX Shift
Description Config signal Pin name Register Values
TX Shift
C25_SHI[0] TX_D(0)[2]/C25_SHI[0] 0x0E01[0] 00 = MII TX signals not delayed
01 = MII TX signals delayed by 10 ns
10 = MII TX signals delayed by 20 ns
11 = MII TX signals delayed by 30 ns
C25_SHI[1] TX_D(0)[3]/C25_SHI[1] 0x0E01[1]
3.2.5 CLK25OUT2 Enable
A 25MHz clock for Ethernet PHYs can be made available by the ET1100 on PDI[31]/CLK25OUT2 pin.
This is only relevant if three MII ports are used. In cases with less than 3 MII ports, pin
LINK_MII(2)/CLK25OUT1 provides CLK25OUT anyway, because LINK_MII(2) is not used. If 4 MII
ports are used, PDI[31]/CLK25OUT2 provides CLK25OUT2 regardless of CLK25OUT2 Enable.
CLK25OUT2 Enable is explained in Table 19.
Table 19: CLK25OUT2 Enable
Description Config signal Pin name Register Values
CLK25OUT2 Enable C25_ENA TX_D(0)[0]/C25_ENA 0x0E01[2]
0 = disable, PDI[31]/CLK25OUT2 is
available for PDI
1 = enable, PDI[31]/CLK25OUT2 is 25
MHz clock output