FIGURES
III-XII
Slave Controller
– ET1100 Hardware Description
FIGURES
Figure 1: ET1100 Block Diagram ............................................................................................................ 1
Figure 2: Frame Processing .................................................................................................................... 2
Figure 3: Mapping of asynchronous µC Interface to Port ...................................................................... 36
Figure 4: Mapping of SPI Interface to Port (1) ....................................................................................... 38
Figure 5: MII Interface signals ............................................................................................................... 43
Figure 6: TX Shift Timing Diagram ........................................................................................................ 45
Figure 7: MII timing RX signals.............................................................................................................. 46
Figure 8: EBUS Interface Signals .......................................................................................................... 47
Figure 9: ET1100 Digital I/O signals ...................................................................................................... 49
Figure 10: Digital Output Principle Schematic ....................................................................................... 51
Figure 11: Bidirectional mode: Input/Output connection (R=4.7 k
Ω recommended) ............................ 51
Figure 12: Digital Input: Input data sampled at SOF, I/O can be read in the same frame .................... 54
Figure 13: Digital Input: Input data sampled with LATCH_IN ................................................................ 54
Figure 14: Digital Output timing ............................................................................................................. 54
Figure 15: Bidirectional Mode timing ..................................................................................................... 54
Figure 16: SPI master and slave interconnection.................................................................................. 55
Figure 17: Basic SPI_DI/SPI_DO timing (*refer to timing diagram for relevant edges of SPI_CLK) .... 61
Figure 18: SPI read access (2 byte addressing, 1 byte read data) with Wait State byte ...................... 62
Figure 19: SPI read access (2 byte addressing, 2 byte read data) with Wait State byte ...................... 63
Figure 20: SPI write access (2 byte addressing, 1 byte write data) ...................................................... 64
Figure 21: SPI write access (3 byte addressing, 1 byte write data) ...................................................... 65
Figure 22: µController interconnection .................................................................................................. 66
Figure 23: Connection with 16 bit µControllers without byte addressing .............................................. 68
Figure 24: Connection with 8 bit µControllers (BHE and DATA[15:8] should not be left open) ............ 69
Figure 25: Read access (without preceding write access) .................................................................... 72
Figure 26: Write access (write after rising edge nWR, without preceding write access) ...................... 72
Figure 27: Sequence of two write accesses and a read access ........................................................... 73
Figure 28: µController interconnection .................................................................................................. 74
Figure 29: Synchronous 32 bit µController connection using Byte Select ............................................ 77
Figure 30: Synchronous 16 bit µController connection using Byte Select ............................................ 78
Figure 31: Synchronous 32 bit µController connection using Transfer Size ......................................... 80
Figure 32: Basic synchronous µController interface timing (*refer to timing diagram for relevant
CPU_CLK_IN edges) ............................................................................................................................ 83
Figure 33: Write access (CS together with TS, Write DATA together with CS, CS and TA on rising
edge) ...................................................................................................................................................... 83
Figure 34: Write access (CS together with TS, Write DATA after CS, CS and TA on rising edge) ...... 83
Figure 35: Write access (CS after TS, Write DATA after CS, CS and TA on rising edge) .................... 84
Figure 36: Read access (CS together with TS, CS and TA on rising edge) ......................................... 84
Figure 37: Read access (CS half a clock period after TS, CS and TA on falling edge) ........................ 84
Figure 38: Sequence of two write accesses and a read access ........................................................... 85
Figure 39: Distributed Clocks signals .................................................................................................... 86
Figure 40: LatchSignal timing ................................................................................................................ 86
Figure 41: SyncSignal timing ................................................................................................................. 86
Figure 42: I²C EEPROM signals ............................................................................................................ 87
Figure 43: Quartz crystal connection ..................................................................................................... 88
Figure 44: Quartz crystal Clock source for ET1100 and Ethernet PHYs .............................................. 88
Figure 45: Oscillator clock source for ET1100 and Ethernet PHYs ...................................................... 89
Figure 46: ET1100 power supply........................................................................................................... 89
Figure 47: Dual purpose configuration input/LED output pins ............................................................... 90
Figure 48: PHY Connection ................................................................................................................... 90
Figure 49: LVDS termination ................................................................................................................. 91
Figure 50: LVDS load resistor ............................................................................................................... 91
Figure 51: Reset Logic .......................................................................................................................... 91
Figure 52: Transparent Mode ................................................................................................................ 92
Figure 53: Reset Timing ........................................................................................................................ 97
Figure 54: Package Outline ................................................................................................................... 99
Figure 55: TFBGA 128 Pin Layout ...................................................................................................... 100
Figure 56: Chip Label .......................................................................................................................... 100
Figure 57: ET100 Tape Information .................................................................................................... 101
Figure 58: Maximum Soldering Profile ................................................................................................ 103
