Artesyn MVME51005E SBC Installation and Use (July 2014) - Manual (Page 122)

Programming the MVME5100
MVME51005E Single Board Computer Installation and Use (6806800A38D) 124
The arbitration assignments for the MVME5100 are shown in below table
7.3.2 Interrupt Handling
The Hawk ASIC, which controls the PHB (PCI Host Bridge) and the MPU/local bus interface
functions on the MVME5100, performs interrupt handling as well. Sources of interrupts may be
any of the following:
 The Hawk ASIC itself (timer interrupts, transfer error interrupts or memory error
interrupts)
 The processor (processor self-interrupts)
 The PCI bus (interrupts from PCI devices)
 The ISA bus (interrupts from ISA devices)
Figure 7-2 illustrates interrupt architecture on the MVME5100. For details on interrupt
handling, refer to the MVME5100-Series Single Board Computer Programmer’s Reference
Guide.
Table 7-4 PCI Arbitration Assignments
PCI Bus Request PCI Master(s)
PIB (Internal) PIB
CPU Hawk ASIC
Request 0 PMC Slot 2
Request 1 PMC Slot 1
Request 2 PCI Expansion Slot
Request 3 Ethernet
Request 4 Universe ASIC (VMEbus)