Artesyn MVME51005E SBC Installation and Use (July 2014) - Manual (Page 118)

Programming the MVME5100
MVME51005E Single Board Computer Installation and Use (6806800A38D) 120
Notes:
1. Programmable via Hawk ASIC.
2. The actual Power Plus II size of each ROM/FLASH bank may vary.
3. The first 1MB of ROM/FLASH Bank A appears at this range after a reset if the rom_b_rv
control bit is cleared. If the rom_b_rv control bit is set, this address maps to ROM/FLASH
Bank B.
4. The only method to generate a PCI Interrupt Acknowledge cycle (8259 IACK) is to perform
a read access to the Hawks PIACK Register at 0xFEFF0030.
5. VME should be placed at the top of PCI memory space.
The following table shows the programmed values for the associated Hawk PCI Host Bridge
Registers for the suggested Processor Memory Map.
FC00 0000 FDFF FFFF 32MB Reserved
Table 7-3 Hawk PPC Register Values for Suggested Memory Map
Address Register Name Register Name
FEFF 0040 MSADD0 X000 F3FF [X:1..8]
FEFF 0044 MSOFF0 & MSATT0 0000 00C2
FEFF 0048 MSADD1 FE00 FE7F
FEFF 004C MSOFF1 & MSATT1 0200 00C0
FEFF 0050 MSADD2 0000 0000
FEFF 0054 MSOFF2 & MSATT2 0000 0000
FEFF 0058 MSADD3 0000 0000
FEFF 005C MSOFF3 & MSATT3 0000 0000
Table 7-2 Suggested CHRP Memory Map
Processor Address
Size Definition Notes
Start End