Artesyn ATCA-F125 Installation and Use Guide (April 2014) - Manual (Page 95)

Functional Description
ATCA-F125 (6873M Artwork) Installation and Use (6806800J94J) 95
The request output signal HRESET_REQ_L of the P2020 QorIQ Integrated Processor indicates
to the board that a condition requiring the assertion of HRST_L has been detected.
HRESET_REQ_L may be activated by a watchdog timer inside the P2020 QorIQ Integrated
Processor, or by software. HRESET_REQ_L may occur at any time synchronous to the core
complex bus clock and stays active until HRST_L is asserted.
The soft reset input signal SRST_L causes a machine check interrupt to both e500 cores of the
P2020 QorIQ Integrated Processor. SRST_L need not to be asserted during a hard reset. SRST_L
may be asserted at any time completely asynchronously.
4.12.1.2 Memory
The registers of a registered DIMM are reset by the DDR_RST_L signal.
4.12.1.3 Onboard Flash
All onboard boot flash devices which are attached to the local bus are reset in parallel when the
HRST_L signal gets asserted.
4.12.1.4 Persistent Memory
The persistent memory is only reset after power-on reset. In all other onboard reset events, the
persistent memory is not reset if the persistent memory feature is enabled.
4.12.2 Ethernet Switch Resets
4.12.2.1 Broadcom BCM56334
A power-on or hard reset is initiated by an active low pulse on the BIX_RST_L signal of the
Broadcom BCM56334 Base Channel Switch. The initialization process loads all the pin
configure modes, clears all switching tables and places the switch in a disabled and idle state.
4.12.2.2 Broadcom BCM56820
A power-on or hard reset is initiated by an active low pulse on the FIX_RST_L signal of the
Broadcom BCM56820 Fabric Channel Switch. The initialization process loads all the pin
configured modes, clears all switching tables and places the switch in a disabled and idle state.