Artesyn ATCA-F125 Installation and Use Guide (April 2014) - Manual (Page 65)

Chapter 4
ATCA-F125 (6873M Artwork) Installation and Use (6806800J94J) 65
Functional Description
4.1 Block Diagram
The following block diagram provides a high level functional view of the ATCA-F125 board and
its interfaces to the front panel, backplane, and RTM.
Figure 4-1 Block Diagram
BC 1[A]
BC 1[B]
IPMC
Backplane
Zone 2 Connectors
FC 1
BC 2
To Other
Hub
Board
To
ShMCs
10/100-T
10/100-T
UART
IPMB-0
Bussed
to
ShMCs/
Blades
Broadcom
56334
24x1G-KX +
4x 10G-XAUI
To Service
Processor
1G-T
TCLK
1/2/3
CLK[1:3][A:B] Bussed
to
Blade
Slots
Broadcom
BCM56820
24x10G-XAUI
+ 4x1G-KX
54680
PHY
54616S
PHY Trans former
AMC Bay
SATA
HDD
SATA
Port 4-7
Port 2
AMC Port 4-7
x2 PCIe
x1 PCIe
Freescale
P2020
Processor
RS232
xcvr
UART
Port 8-11
UC[2]
14x 10G-BX4/XAUI
10 10 10 10 10 10 10 10 10 10 10 10 10 10
Backplane Zone 2 Connectors
Logical Slot 3 4 5 6 7 8 9 10 11 12 13 14 15 16
To Zone 3 Connector To Zone 3 Connector
2x 10G-XAUI BCM8747
2xXAUI<>
SFI
SFI
RJ45
1G-SGMII
1G-SGMII BIX MUX 1
To Zone 3 Connector
Clock FPGA
Semtech
TopSync
MLVDS
3/3E
Oscillator
Maxim
26503
Framers
2x BITS/SSU
Trans formers
Maxim
26503
Framers Trans formers
2x
RJ45
1G-SGMII
1G-SGMII
TopSync Base
2x 10G-
XAUI
BCM8747
2xXAUI<>
SFI BIX
SFP+
BIX
SFP+
UC[0:1]
Port 0
Port 1
1G-BX/KX(SERDES)
Base X-Connect:
Tx to UC[1]; Rx to UC[0]
Base X-Connect:
Tx to UC[0]; Rx to UC[1]
1G-SGMII
to AMC Port 11
Port 8
1G-SGMII
to AMC Port 9
to AMC Port 10
2x1GbE
MAC/PHY
5709S
PCI-E x4
10G-XAUI
AMC Port 1
AMC Port 8-11
6x 10G-XAUI To Zone 3 Connector
10G-XAUI
2x 10G-XAUI To Zone 3 Connector
DIMM1
DDR3
w/ ECC
SATA
Bridge
x1 PCIe
12x 1G-SGMII
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1000BASE-KX
Backplane Zone 2 Connectors 14x 1G-T
Logical Slot 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Transformers
54680
PHYs 2x 1G-SGMII
1G-SGMII
1G-SGMII
AMC Port 1
To Zone 3
Connector
To Zone 3
Connector
AMC=>Base X-Connect
AMC=>Fabric X-Connect
Fabric=>AMC X-Connect
UC[3:4] Fabric X-Connect:
Tx to UC[4]; Rx to UC[3]
Fabric X-Connect:
Tx to UC[3]; Rx to UC[4] AMC=>Fabric X-Connect
Fabric=>AMC X-Connect
AMC=>Base X-Connect
SATA
1G-SGMII
1G-SGMII
4x 1G-SGMII
Trans formers
1G-SGMII
1G-SGMII
UART to IPMC
1G-SGMII Boot+Kernel
NOR Flash
Local Bus
Boot+Kernel
NOR Flash
USB
PHY
FileSystem
NAND Flash
5x Inter-Shelf Synch 6x
RJ45
MLVDS
Master/Slave Synch
GPS ToD (RS232)
GPS 1pulse-per-second
SPI to Processor
10/100 to Base/Fabric
TopSync Base
From Zone 3 Connector
BIX MUX 1
BIX MUX 2
RGMII
54616S
1G-T
RJ45
+
MAG
HUB USB
FIX
SFP+
FIX
SFP+
Front Panel
ARTM-F125
FIX
SFP+
FIX
SFP+ BCM8747
4xXAUI<>
SFI FIX
SFP+
FIX
SFP+
FIX
SFP+
FIX
SFP+
BIX
SFP+
BIX
SFP+
BIX
SFP
BIX
SFP
BIX
SFP
BIX
SFP
2x 10G-XAUI
2x 10G-XAUI
4x 10G-XAUI
4x 1G-SGMII
SFI
SFI
SFI
SFI
SFI
SFI
SFI
SFI
SFI
SFI
SFI
FPGA
BCM8747
4xXAUI<>
SFI
DIMM2
DDR3
w/ ECC
Clock Distribution
25MHZ
100MHz PCIE
156.25MHz
100MHz
125MHz
Input
PWR
Module
-48VDC
12V
Module
+3.3V_MGT
5V 3.3V 2.5V 1.8V 1.5V
1.25V 1.2V 1.0V 1.05V
Hot
Swap
JTAG
Controller
B2
P20-P23
P0-P3
P5-P9
P14
P12-P13
GE0
GE1
P15
GE3
GE2
P16-P19
P10-P11
P4
1
B2 B1
2
B2
A
B1
A 3
B2
B1
A
4
A
B2
B1
5 A
B2
B1
6 A
B1
B2
7 B1
B2
P1
P0
A
B2
8
A
B1
B2
BIX MUX 2
9 10
A
B1
B2
A
B1
B2
11
A
B2
B1
HG2-HG3
P0-
P11
P12-P13
P17
P18
HG0-
HG1
P19
P16
P14
P15
12
13
A
A
B1
B2
B1
14
B1
B2
A
15
B1 B2
A
A
A
B1
B2
B2
B1
5482S
RGMII
UC[2]
UC[2]
54616S
PHY
Trans former
5241
PHY SGMII
B2
1000Base-X
P20-
P23
+3.3V
+12V
156.25MHz
+3.3V
+12V
AMC Port 4-7
To Zone 3
Connector
ETH3
ETH4
ETH1
ETH2
ETH12
ETH11
ETH10
ETH9
ETH8
ETH7
ETH6
ETH5
ETH1
ETH2
ETH3
ETH4
ETH5
CONSOLE
USB
TE1 TE2
MS EXT1
EXT2 EXT3
EXT4 EXT5 SMA 10MHz
SMA 1PPS
RJ45 Time-of-Day
TOD
1PPS
10MHz
RGMII 1G-SGMII
To Zone 3 Connector