Artesyn ATCA-F125 Installation and Use Guide (April 2014) - Manual (Page 110)

U-Boot
ATCA-F125 (6873M Artwork) Installation and Use (6806800J94J) 110
5.8.2 Controlling the Execution of the POST
The environment variable post_control allows to configure when POST is executed.
Possible values of post_control and their meaning are described in the following table.
FPGA Register sanity check. The version code is checked. It
must not be 0x00 or 0xFF.
DRAM Address line and data-line test.
Switch devices The PCI interface is checked as follows:

Check for configuration space access
(vendor/device ID)
 Perform walking-one test on first memory-
mapped register
Base interface
extender/SPI Data test on LED register page 0, offset 0x12
I2C buses Check whether bus addresses 0x50,0x51, 0x52 are
accessible on bus 0 and 0x50, 0x6E on bus 1.
RTC Checks whether the second counter is advancing.
Compares the number of CPU ticks in one second
against the expected system clock frequency (66 MHz)
MDIO/PHY Attempts to read model and device ID from PHY address
0..3
TSEC network port The PHY for each TSEC port is configured to loop back
mode, 100 and 1000 MBPS, and 10000 loop back
packets are sent and verified.
Boot flash Flash devices are sent into CFI query mode and the
query string is verified.
RTM Check connectivity of 10G repeater devices on RTM
Table 5-6 POST Routines (continued)
Device Description
Table 5-7 Environment Variable post_control
Value Description
off
Disables POST altogether