Artesyn ATCA-F125 Installation and Use Guide (April 2014) - Manual (Page 72)

Functional Description
ATCA-F125 (6873M Artwork) Installation and Use (6806800J94J) 72
 Interrupt Routing Unit
 Reset Controller
 Local Bus to SPI Interface
 Telecom Clocking Support
 Service Processor Watchdog Timer
4.5.1 Serial Configuration PROM
The FPGA is configured at power up by loading the contents of an Atmel AT45DB041 SPI PROM
device. This configuration uses standard SPI Flashes for the FPGA configuration. For fault
recovery during the remote upgrade of the FPGA PROM, the ATCF125 board will provide a
backup SPI device. Both PROMs will be programmed with identical images during the
production process. The IPMI infrastructure can be used to select the secondary boot device.
The primary PROM device is selected by default.
The SPI device chain will also include the SPI device for the BCM8747 microcode so that it can
be upgraded by the service processor.
There are four different modes of operation for the FPGA and the SPI flash devices:
 FPGA Configuration - The FPGA automatically controls the CSO_B, CCLK and MOSI pins
and reads the configuration data over DIN. Whether the configuration data is supplied by
SPI Flash 1 or 2 is determined by the routing of the CSO_B signal which is controlled by the
IPMC. AUX_SS is deasserted by virtue of the fact the FPGA is not configured.
 Configuration Flash programming - A SPI controller in the FPGA (driven by the service
processor over the local bus) controls CSO_B, CCLK and MOSI, and monitors DIN. The IPMC
has to select the chip select routing for the primary SPI device. The secondary SPI device,
which is for fail-safe backup purposes only, is write protected and cannot be programmed
in the field through the FPGA SPI interface. AUX_SS is deasserted by the SPI controller.