Artesyn ATCA-F125 Installation and Use Guide (April 2014) - Manual (Page 109)

U-Boot
ATCA-F125 (6873M Artwork) Installation and Use (6806800J94J) 109
5.8.1 POST Routines
The following table describes that POST routines are performed.
0x02 Memory error. The address and data line test failed.
0x0b U-boot image CRC mismatch detected
0x0D Wrong CPU speed
0xfd Artesyn Embedded Technologies specific POST
error code. For more information, see
Table "SYS
FW PROGRESS IPMI Sensor - POST Error Event
Codes" on page 109
.
0x00 One of the remaining POST errors was detected.
Table 5-5 SYS FW PROGRESS IPMI Sensor - POST Error Event Codes
Event Data (Byte 3) Description
0x1E Error accessing the switch devices
0x03 Error in network loop back test
0x20 Error in network PHY test
0x1F Error in glue logic (FPGA) test
0x0A Error in I2C bus test
0x16 Error in RTC test
0x09 Error in flash test
0x21 Error in CPU test
0x22 Error in PCI bus test
Table 5-4 Post Results in SYS FW PROGRESS IPMI Sensor Reading Data (continued)
Value Description
Table 5-6 POST Routines
Device Description
CPU Check PLL configuration (PORPLLSR register).
Check device configuration (PORDEVSR register)