Artesyn ATCA-F125 Installation and Use Guide (April 2014) - Manual (Page 71)

Functional Description
ATCA-F125 (6873M Artwork) Installation and Use (6806800J94J) 71
The IPMC building block is designed to keep the payload running even during firmware
upgrade. When the payload is powered off, hot plug compatible buffers are used on signals
which bridge the management power domain and the payload power domain to prevent
leakage currents to the payload power domain. In case of an IPMC firmware upgrade, the
output signals to the payload remain unchanged. After IPMC firmware update is finished, the
IPMC reads status of the signals before driving them again.
4.4.1 Temperature Sensors
The on board temperature sensors are implemented using National LM75 digital temperature
sensors. The following table provides the location, the upper non critical, critical and non
recoverable temperature thresholds for each of the onboard temperature sensors. These
thresholds will be determined by correlating the sensor temperature to the critical component
temperature during thermal testing.
4.5 FPGA
A Xilinx XC3S700A Spartan 3A family FPGA is used on the board to provide a combination of
glue logic functions and telecom clock support functions. The FPGA functions include the
following:
 Local Bus Interface
 Local Bus Address Latch and Decoder
 Low Pin Count Interface between Host and IPMC
Table 4-1 Temperature Sensors
Device Temperature Thresholds
Lower Non
Critical
Lower
Critical Lower Non
Recoverable Upper Non
Critical Upper
Critical Upper Non
Recoverable
Air Inlet Component Side
1 0 C -5 C -10 C 54 C 61 C 72 C
BIX (BCM56334) 0 C -5 C -10 C 50 C 100 C 115 C
FIX (BCM56820) 0 C -5 C -10 C 55 C 100 C 115 C
SP (P2020) 0 C -5 C -10 C 50 C 100 C 115 C