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Figure 12. FT Router 5000 Chip Pinout
Table 9 lists the pin assignments for the FT Router 5000 chip. All digital inputs are low-
voltage transistor-transistor logic (LVTTL) compatible, 5 V tolerant, with low leakage. All
digital outputs are slew-rate limited to reduce Electromagnetic Interference (EMI) concerns. Table 9. FT Router 5000 Chip Pin Assignments
Name
Pin
Number Type
Description
SVC~
1
Digital I/O
Service (active low)
IO0
2
IO0 (side A to side B)
IO1
3
IO1 (side A to side B)
IO2
4
IO2 (side A to side B)
IO3
5
IO3 (side A to side B)
VDD1V8
6
Power
1.8 V Power Input
(from internal voltage regulator)
IO4
7
IO4 (side A to side B)
VDD3V3
8
3.3 V Power
IO5
9
IO5 (side A to side B)
IO6
10
IO6 (side A to side B)
IO7
11
IO7 (side A to side B)
IO8
VDDPLL
GNDPLL
VOUT1V8
RST~
VIN3V3
AVDD3V3
NETN
AGND
NETP
NC
GND
IO
VDD
V
TRST
~
TCK
TMS
TDI
TDO
XIN
XOUT
TXON
RXON
CP
CS
0
SDA
_
SCL
MISO
SCK
MOSI
37
38
39
40
41
42
43
44
45
46
47
48
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GND PAD
FT Router 5000
®
L
ON
W
ORKS
Router User’s Guide
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