Jtag interface (tck, tdi, tdo, tms, and trst~), Power and ground – Echelon LonWorks Router User Manual

Page 47

JTAG Interface (TCK, TDI, TDO, TMS, and
TRST~)

All Series 5000 chips (including the Router 5000 and FT Router 5000) provide an

interface for the Institute of Electrical and Electronics Engineers (IEEE)

Standard Test Access Port and Boundary-Scan Architecture (IEEE 1149.1-1990)

of the Joint Test Action Group (JTAG) to allow a Series 5000 chip to be included

in the boundary-scan chain for device production tests.
See the Series 5000 Chip Data Book for more information about the JTAG pins

for a Series 5000 chip, including the Router 5000 and FT Router 5000.

Memory Interface (CS0~, MISO, MOSI, SCK,
SCL, and SDA_CS1~)

The interface for accessing off-chip non-volatile memory (NVM) is a serial

interface that follows either of the following protocols: serial Inter-Integrated

Circuit (I

C) or serial peripheral interface (SPI). Although a Series 5000 chip

supports both Electrically Erasable Programmable Read-Only Memory

(EEPROM) devices and flash memory devices, a typical Router 5000 or FT Router

5000 device uses a single 2 KB EEPROM device (using either the I

C protocol or

the SPI protocol). This EEPROM device contains configuration data for the

router. If you supply an EEPROM device larger than 2 KB, the additional

memory space is not used.
Recommendation: Your router design should allow for in-circuit

programmability of the serial EEPROM device, unless the EEPROM devices

must be programmed before device assembly.
See the Series 5000 Chip Data Book for more information about how to use the

memory interface pins for a Series 5000 chip, including the Router 5000 and FT

Router 5000.

Power and Ground

Connect the VDD3V3 pins (8, 18, 29, 30, 41, and 42) to V

DD33

. Also connect the

AVDD3V3 pin (31) to an analog V

DD33

source, if different from the digital V

DD33

source. In general, the VDD3V3 pins and the AVDD3V3 pin connect to the

same V

DD33

source.

The VOUT1V8 pin (27) is the output of the on-chip voltage regulator. Connect

the VDD1V8 pins (6, 16, and 44) to the VOUT1V8 pin (27) to connect the 1.8 V

input pins to the output of the internal voltage regulator.
Important: Do not connect an external 1.8 V source to any of the VDD1V8 pins

(6, 16, and 44). Connect these pins to the VOUT1V8 pin (27) only. Using an

external 1.8 V source voids the warranty for the chip, and can cause

unpredictable and possibly irreparable results.
Connect the VDDPLL pin (25) to the VOUT1V8 pin (27), with an associated chip

ferrite bead. Connect the GNDPLL pin (26) to GND, with an associated chip

ferrite bead.
Connect the GND pin (36) and the chip’s pad (pin 49) to logic ground. Also

connect the AGND pin (33) to logic ground.

ORKS

Router User’s Guide