Maxim Integrated MAXQ Family Users Guide: MAXQ2000 Supplement - Manual (Page 43)

Register Name: PO7
Register Description: Port 7 Output Register
Register Address: M1[03h]
Bits 0 and 1: (PO7.0 and PO7.1) Port Output for P7.0 and P7.1. This register stores the data that will be output on any of the pins of
Port 7 that have been defined as output pins. If the port pins are in input mode, this register controls the weak pullup for each pin.
Changing the data direction of any pins for this port (through register PD7) will not affect the value in this register.
Bits 2 to 7: (PO7.2 to PO7.7) Reserved
Register Name: EIF1
Register Description: External Interrupt Flag 1 Register
Register Address: M1[06h]
Each bit in this register is set when a negative or positive edge (depending on the ITn bit setting) is detected on the corresponding
interrupt pin. Once an external interrupt has been detected, the interrupt flag bit will remain set until cleared by software or a reset.
Setting any of these bits will cause the corresponding interrupt to trigger if it is enabled to do so.
Bit 0: (EIF1.0) External Interrupt 8 Edge Detect (IE8)
Bit 1: (EIF1.1) External Interrupt 9 Edge Detect (IE9)
Bit 2: (EIF1.2) External Interrupt 10 Edge Detect (IE10)
Bit 3: (EIF1.3) External Interrupt 11 Edge Detect (IE11)
Bit 4: (EIF1.4) External Interrupt 12 Edge Detect (IE12)
Bit 5: (EIF1.5) External Interrupt 13 Edge Detect (IE13)
Bit 6: (EIF1.6) External Interrupt 14 Edge Detect (IE14)
Bit 7: (EIF1.7) External Interrupt 15 Edge Detect (IE15)
MAXQ Family User’s Guide:
MAXQ2000 Supplement
Bit # 7 6 5 4 3 2 1 0
Name — — — — — — PO2.1 PO2.0
Reset 0 0 0 0 0 0 1 1
Access r r r r r r r/w r/w
Bit # 7 6 5 4 3 2 1 0
Name IE15 IE14 IE13 IE12 IE11 IE10 IE9 IE8
Reset 0 0 0 0 0 0 0 0
Access r/w r/w r/w r/w r/w r/w r/w r/w
Maxim Integrated 43