Maxim Integrated MAXQ Family Users Guide: MAXQ2000 Supplement - Manual (Page 25)

Bit 3: (CKCN.3) Switchback Enable (SWB). Setting this bit to 1 enables Switchback mode. If power management mode (either divide
by 256 or 32kHz) is active and Switchback is enabled, the PMME bit will be cleared to 0 when any of the following conditions occur.
• An external interrupt is generated based on an edge detect.
• Either serial port 0 or serial port 1 is enabled to receive data and detects a low condition on its data receive pin.
• Either serial port 0 or serial port 1 is enabled to transmit data has a byte written to its buffer register by software.
• The SPI module is enabled in slave mode and receives a slave select signal from the bus master.
• The SPI module is enabled to transmit data and has a byte written to its buffer register by software.
• A time-of-day interrupt occurs from the real-time clock.
• Debug mode is entered through command entry or a breakpoint match.
Triggering a Switchback condition only clears the PMME bit; the settings of CD0 and CD1 remain the same. This means that exiting
Switchback from divide-by-256 mode will revert to a divide by 1 mode, while exiting Switchback from 32kHz mode will revert to a divide
by 8 mode.
When either power management mode is active, the SWB bit may not be set to 1 as long as any of the above conditions are true.
Bit 4: (CKCN.4) Stop Mode Select (STOP). Setting this bit to 1 causes the processor to enter Stop Mode. This will not change the cur-
rently selected clock divide ratio.
Bit 5: (CKCN.5) Ring Oscillator Mode (RGMD). This read-only bit indicates the current oscillator source. If RGMD is set to 1, the inter-
nal ring oscillator is currently acting as the oscillator source for the system clock. (This can either be because RGSL = 1, or because
RGSL = 0, and the crystal warmup period has not yet completed.) If RGMD is cleared to 0, the external crystal oscillator is currently
acting as the oscillator source for the system clock (unless the PMM2 32kHz mode is active).
Bit 6: (CKCN.6) Ring Oscillator Select (RGSL). If this bit is set to 1, the ring oscillator will immediately begin sourcing the system
clock, and the high-frequency oscillator will be disabled (unless 32kHz mode and Switchback are enabled). Clearing this bit to 0
enables the high-frequency oscillator. Until the warmup period for the high-frequency oscillator has completed, the ring oscillator will
still provide the system clock source (indicated by RGMD = 1). Once the warmup period completes, the system clock source will auto-
matically switch over to the high-frequency oscillator, and RGMD will go to 0.
Bit 7: (CKCN.7) Reserved
MAXQ Family User’s Guide:
MAXQ2000 Supplement
Maxim Integrated 25