Maxim Integrated MAXQ Family Users Guide: MAXQ2000 Supplement - Manual (Page 18)

MAXQ Family User’s Guide:
MAXQ2000 Supplement
This power management mode is entered by setting the PMME bit (CKCN.2) to 1 while the CD1 and CD0 (CKCN[1:0]) bits are both
cleared to 0. When PMM1 mode is exited (either by clearing the PMME bit or as a result of a switchback trigger), system operation will
revert to the mode indicated by the values of the CD1 and CD0 bits, which in this case will be the standard divide-by-1 clock mode.
32kHz Mode (PMM2)
In this power management mode, all operations continue as normal using the 32kHz clock as the system clock source. This power
management mode affects module clock rates as follows.
• Program execution occurs at the 32kHz clock rate.
• The RTC module continues to operate using its originally selected clock, which is either the 32kHz clock or the high-frequency clock
divided by 128, as selected by the ACS bit (RCNT.13).
• The LCD module continues to operate using its originally selected clock, which is either the 32kHz clock or the high-frequency clock
divided by 128, as selected by the LCCS bit (LCRA.6).
• All other functional modules (timers, UARTs, SPI) operate at the 32kHz clock rate.
This power management mode is entered by setting the PMME bit (CKCN.2) to 1 while the CD1 and CD0 (CKCN[1:0]) bits are both
set to 1. When PMM2 mode is exited (either by clearing the PMME bit or as a result of a switchback trigger), system operation will revert
to the mode indicated by the values of the CD1 and CD0 bits, which in this case will be the divide-by-8 clock mode.
When PMM2 mode is entered, the high-frequency oscillator is automatically disabled unless Switchback has been enabled by setting
the SWB bit to 1. If Switchback is not being used, the LCD module and RTC module should both be set to use the 32kHz clock (not
HFClk / 128) before PMM2 mode is entered.
Switchback Mode
As described in the MAXQ Family User’s Guide, Switchback mode provides automatic exit from power management mode when a
higher clock rate is required to respond to I/O, such as UART activity, SPI activity, or an external interrupt.
Switchback mode is enabled when the SWB (CKCN.3) bit is set to 1 and the PMME (CKCN.2) bit is set to 1(the system is in either the
PMM1 or PMM2 modes). If Switchback is enabled, the PMME bit will be cleared (causing the system to exit power management mode)
when any of the following conditions occur.
• An external interrupt condition occurs on an INTx pin and the corresponding external interrupt is enabled.
• An active-low transition occurs on the RXD0 or RXD1 pin and the corresponding UART is enabled to receive data. If PMM2 mode is
exited in this manner, the first character read by the UART will be received incorrectly.
• The SBUF0 or SBUF1 register is written to transmit a byte and the corresponding UART is enabled to transmit data.
• The SPIB register is written to send an outgoing byte through the SPI interface and transmission is enabled.
• An active-low transition occurs on the SSEL pin when the SPI interface is configured for slave mode.
• A Time-of-Day alarm is generated by the RTC module.
• Active debug mode is entered either by a breakpoint match or direct issuance of the Debug command from background mode.
As described in the MAXQ Family User’s Guide, if any of these conditions are true (a Switchback source is active) and the SWB bit has
been set, the PMME bit cannot be set to enter power management mode.
Stop Mode
Stop mode disables all circuits within the MAXQ2000 except for the 32kHz crystal amplifier and any circuitry that is clocked directly
by the 32kHz clock. All other on-chip clocks, timers, serial ports, and other peripherals are stopped, and no code execution occurs.
Once in Stop mode, the MAXQ2000 is in a mostly static state, with power consumption determined largely by leakage currents.
Stop mode is invoked by setting the STOP bit to 1. The MAXQ2000 enters Stop mode immediately when the STOP bit is set. Entering
Stop mode does not affect the setting of the clock control bits; this allows the system to return to its original operating frequency fol-
lowing Stop mode removal.
The processor exits Stop mode if any of the following conditions occur.
• External reset (from the RST pin)
• Power-on reset
• External interrupt (interrupt must be enabled prior to entering Stop mode)
• RTC time-of-day alarm
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