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Maxq family user’s guide: maxq2000 supplement – Maxim Integrated MAXQ Family Users Guide: MAXQ2000 Supplement User Manual

Page 42

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MAXQ Family User’s Guide:

MAXQ2000 Supplement

Register Name:

PO4

Register Description:

Port 4 Output Register

Register Address:

M1[00h]

Bits 0 to 4: (PO4.0 to PO4.4) Port 4 Output. This register stores the data that will be output on any of the pins of Port 4 that have been
defined as output pins. If the port pins are in input mode, this register controls the weak pullup for each pin. Changing the data direc-
tion of any pins for this port (through register PD4) will not affect the value in this register.

Bits 5 to 7: (PO4.5 to PO4.7) Reserved

Register Name:

PO5

Register Description:

Port 5 Output Register

Register Address:

M1[01h]

Bits 0 to 7: (PO5.0 to PO5.7) Port 5 Output. This register stores the data that will be output on any of the pins of Port 5 that have been
defined as output pins. If the port pins are in input mode, this register controls the weak pullup for each pin. Changing the data direc-
tion of any pins for this port (through register PD5) will not affect the value in this register.

Register Name:

PO6

Register Description:

Port 6 Output Register

Register Address:

M1[02h]

Bits 0 to 7: (PO6.0 to PO6.7) Port 6 Output. This register stores the data that will be output on any of the pins of Port 6 that have been
defined as output pins. If the port pins are in input mode, this register controls the weak pullup for each pin. Changing the data direc-
tion of any pins for this port (through register PD6) will not affect the value in this register.

Bit #

7

6

5

4

3

2

1

0

Name

PO2.4

PO2.3

PO2.2

PO2.1

PO2.0

Reset

0

0

0

1

1

1

1

1

Access

r

r

r

r/w

r/w

r/w

r/w

r/w

Bit #

7

6

5

4

3

2

1

0

Name

PO5.7

PO5.6

PO5.5

PO5.4

PO5.3

PO5.2

PO5.1

PO5.0

Reset

1

1

1

1

1

1

1

1

Access

r/w

r/w

r/w

r/w

r/w

r/w

r/w

r/w

Bit #

7

6

5

4

3

2

1

0

Name

PO6.7

PO6.6

PO6.5

PO6.4

PO6.3

PO6.2

PO6.1

PO6.0

Reset

1

1

1

1

1

1

1

1

Access

r/w

r/w

r/w

r/w

r/w

r/w

r/w

r/w

Maxim Integrated

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