Maxim Integrated MAXQ Family Users Guide: MAXQ2000 Supplement - Manual (Page 13)

To select the ring oscillator as the system clock source, the RGSL bit (CKCN.6) must be set to 1. Setting this bit immediately switches
over the system clock source to the ring oscillator. The RGMD (CKCN.5) bit indicates the current system clock source. If the ring oscil-
lator is currently providing the system clock, RGMD equals 1; otherwise, RGMD equals 0.
Because the RGSL bit is cleared by power-on reset only, if this bit is set before entering Stop mode, the ring oscillator will still be used
as the system clock source when Stop mode is exited. In this case, a 4-cycle warmup delay is required when exiting Stop mode before
execution resumes using the ring oscillator as the system clock source.
When the system clock source is switched back from the ring oscillator to the high-frequency oscillator by clearing RGSL to zero, the
ring oscillator will still be used as the system clock source until the warmup period has completed for the high-frequency oscillator. This
will be reflected by the value of the RGMD bit, which remains at 1 until the warmup for the high-frequency oscillator has completed
and the clock switches over, at which point RGMD switches to 0.
External 32kHz Crystal Oscillator Circuit or Clock
The MAXQ2000 provides a 32kHz clock for use by the real-time clock module. This clock can be generated either by the internal 32kHz
crystal oscillator (using an external crystal) or by an external source. The 32kHz clock is also usable as a system clock source, a clock
for the LCD controller, and as an alternate Timer 2 clock.
The 32kHz crystal amplifier is switched off by default on power-on reset. With this crystal amplifier disabled, the 32kHz clock must be
provided directly by an external source. To use the 32kHz crystal amplifier to generate the 32kHz clock, the amplifier must be turned
on by setting the X32D (RCNT.14) bit to 0 and a 32.768kHz, 6pF crystal should be connected between the 32KIN and 32KOUT pins.
To use the 32kHz clock as a source for the system clock, Power Management Mode 2 must be entered by setting PMME, CD1, and
CD0 to 1. See the Power Management Features section for more details.
Interrupts
In general, interrupt handling on the MAXQ2000 operates as described in the MAXQ Family User’s Guide. All interrupt sources have
the same priority, and all interrupts cause program execution to branch to the location specified by the Interrupt Vector (IV) register,
which defaults to 0000h.
Table 2 lists all possible interrupt sources for the MAXQ2000, along with their corresponding module interrupt enable bits, local inter-
rupt enable bits, and interrupt flags.
• Each module interrupt enable bit, when cleared to 0, will block interrupts originating in that module from being acknowledged.
When the module interrupt enable bit is set to 1, interrupts from that module are acknowledged (unless the interrupts have been
disabled globally).
• Each local interrupt enable bit, when cleared to 0, will disable the corresponding interrupt. When the local interrupt enable bit is set
to 1, the interrupt will be triggered whenever the interrupt flag is set to 1 (either by software or hardware).
• All interrupt flag bits cause the corresponding interrupt to trigger when the bit is set to 1. These bits are typically set by hardware
and must be cleared by software (generally in the interrupt handler routine).
Note that for an interrupt to fire, the following five conditions must exist:
• Interrupts must be enabled globally by setting IGE (IC.0) to 1.
• The module interrupt enable bit for that interrupt source’s module must be set to 1.
• The local interrupt enable bit for that specific interrupt source must be set to 1.
• The interrupt flag for that interrupt source must be set to 1. Typically, this is done by hardware when the condition that requires inter-
rupt service occurs.
• The Interrupt In Service (INS) bit must be cleared to 0. This bit is set automatically upon vectoring to the interrupt handler (IV) address
and cleared automatically upon exit (RETI/POPI), so the only reason to clear this bit manually (inside the interrupt handler routine) is
to allow nested interrupt handling.
MAXQ Family User’s Guide:
MAXQ2000 Supplement
Maxim Integrated 13