Altera LVDS SERDES Transmitter / Receiver - Manual (Page 8)

Figure 5: IP Core Generated Files
Notes:
1. If supported and enabled for your IP variation
2. If functional simulation models are generated
3. Ignore this directory
<your_ip>.v or .vhd - Top-level IP synthesis file
_inst.v or .vhd - Sample instantiation template
.bsf - Block symbol schematic file
.vo or .vho - IP functional simulation model 2
_syn.v or .vhd - Timing & resource estimation netlist1
_bb.v - Verilog HDL black box EDA synthesis file
.qip - Quartus II IP integration file
greybox_tmp
3
.cmp - VHDL component declaration file
Upgrading IP Cores
IP core variants generated with a previous version of the Quartus II software may require upgrading
before use in the current version of the Quartus II software. Click Project > Upgrade IP Components to
identify and upgrade IP core variants.
The Upgrade IP Components dialog box provides instructions when IP upgrade is required, optional, or
unsupported for specific IP cores in your design. You must upgrade IP cores that require it before you can
compile the IP variation in the current version of the Quartus II software. Many Altera IP cores support
automatic upgrade.
The upgrade process renames and preserves the existing variation file (
.v
, .
sv
, or
.vhd
) as
_
BAK.v , .sv , .vhd in the project directory.
Table 4: IP Core Upgrade Status
IP Core Status Corrective Action
Required Upgrade IP
Components
You must upgrade the IP variation before compiling in the current version of
the Quartus II software.
Optional Upgrade IP
Components
Upgrade is optional for this IP variation in the current version of the Quartus
II software. You can upgrade this IP variation to take advantage of the latest
development of this IP core. Alternatively you can retain previous IP core
characteristics by declining to upgrade.
8 Upgrading IP Cores
UG-MF9504
2014.12.15
Altera Corporation LVDS SERDES Transmitter/Receiver IP Cores User Guide
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