Altera LVDS SERDES Transmitter / Receiver - Manual (Page 16)

Option Description
What is the clock resource used for 'tx_
coreclock'?
Specifies the clock resource type fed to the
tx_coreclock
signal. Allowed values are Auto selection (the Compiler
determines the type), Global clock, and Regional clock.
The default value is Auto selection.
Simulation Model (page 6)
Simulation Libraries
Specifies the libraries needed for functional simulation by
third-party tools.
Generate netlist Specifies whether to turn on the option to generate synthesis
area and timing estimation netlist.
Summary (page 7)
Summary
Specifies the types of files to be generated. A gray checkmark
indicates a file that is automatically generated; a green
checkmark indicates an optional file.
Choose from the following types of files:
• AHDL Include file (.inc)
• VHDL component declaration file (.cmp)
• Quartus II symbol file (.bsf)
• Instantiation template file (_inst.v or
>_inst.vhd
• Verilog HDL block box file (_bb.v)
• Pin Planner File (_.ppf)
If you turn on the Generate netlist option, the file for that
netlist is also available (_syn.v).
Related Information
• Introduction to Altera IP Cores
ALTLVDS_RX Parameter Settings
On the General page (page 3) of the parameter editor, depending on the device you selected, you can
configure the following options:
• Implement the SERDES circuitry in LEs (logic cells) or dedicated SERDES
• Use internal PLL or external PLL
• Use DPA mode or non-DPA mode
The selections you make on the General page determine the features available on the remaining pages of
the parameter editor.
The following table lists the parameter settings for the LVDS receiver IP core.
16 ALTLVDS_RX Parameter Settings
UG-MF9504
2014.12.15
Altera Corporation LVDS SERDES Transmitter/Receiver IP Cores User Guide
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