Altera LVDS SERDES Transmitter / Receiver - Manual (Page 24)

Option Description
Align data to the rising edge of clock When you turn on this option, the data path is registered on
the positive edge of the
diffioclk
signal (also referred to as
the LVDS clock). When you turn off this option, the data path
is registered on the negative edge of the
diffioclk
signal. This
option is available only if you use a dedicated SERDES block,
and is available only in non-DPA mode.
This option changes the phase that captures the received data
by 180°. Use caution when you turn off this option. The phase
shift of the capture clock is automatically set according to the
setting for the What is the phase alignment of 'rx_in' with
respect to the rising edge of 'rx_inclock'? (in degrees) option.
Changing the phase of the capture clock can lead to data
corruption. If you turn off this option, the LVDS data is aligned
to the falling edge of the clock.
For an example, if you have two receivers interface with
identical parameters except for the
rx_in
signal relationship to
the
rx_inclock
signal, and you want to merge PLLs, one
interface must have a 0° (rising edge) alignment, and the
second interface must have a 180° (falling edge) alignment. You
can only merge the PLLs when they have the same clock and
phase settings; both must be set with the same alignment. You
can set both receivers to be 0° aligned, and turn off Align data
to the rising edge of clock on the 180° aligned interface.
Use 'rx_coreclk' input port This option is enabled when the LVDS is implemented in logic.
When you turn on this option, it adds an input port, which
when asserted performs an asynchronous reset of all the logic
in the ALTLVDS_RX IP core excluding the PLL.
Use 'rx_channel_data_align' input port Turn on this option to control bit insertion on a channel-by-
channel basis to align the word boundaries of the incoming
data. The data slips one bit for every pulse on the
rx_channel_
data_align
port. This option is available only if you use a
dedicated SERDES block.
You can use control characters in the data stream so your logic
can have a known pattern to search for. You can compare the
data received for each channel, compare to the control
character you are looking for, then pulse the
rx_channel_
data_align
port as required until you successfully receive the
control character.
To use this port, you must meet the following requirements:
• The minimum pulse width is one period of the parallel clock
in the logic array (
rx_outclock
).
• The minimum low time between pulses is one period of the
parallel clock.
• There is no maximum high or low time.
• Valid data is available on the third parallel clock cycle after
the rising edge of the
rx_channel_data_align
signal.
24 ALTLVDS_RX Parameter Settings
UG-MF9504
2014.12.15
Altera Corporation LVDS SERDES Transmitter/Receiver IP Cores User Guide
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