Altera LVDS SERDES Transmitter / Receiver User Manual
Page 66
You can use the functional simulation model and the testbench or example design generated with your IP
core for simulation. The functional simulation model and testbench files are generated in a project
subdirectory. This directory may also include scripts to compile and run the testbench. For a complete list
of models or libraries required to simulate your IP core, refer to the scripts generated with the testbench.
You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts.
NativeLink launches your preferred simulator from within the Quartus II software.
Figure 16: Simulation in Quartus II Design Flow
Post-fit timing
simulation netlist
Post-fit timing
simulation
(3)
Post-fit functional
simulation netlist
Post-fit functional
simulation
Analysis & Synthesis
Fitter
(place-and-route)
TimeQuest Timing Analyzer
Device Programmer
Quartus II
Design Flow
Gate-Level Simulation
Post-synthesis
functional
simulation
Post-synthesis functional
simulation netlist
(Optional) Post-fit
timing simulation
RTL Simulation
Design Entry
(HDL, Qsys, DSP Builder)
Altera Simulation
Models
EDA
Netlist
Writer
Note: Post-fit timing simulation is not supported for 28nm and later device archetectures. Altera IP
supports a variety of simulation models, including simulation-specific IP functional simulation
models and encrypted RTL models, and plain text RTL models. These are all cycle-accurate
models. The models support fast functional simulation of your IP core instance using industry-
standard VHDL or Verilog HDL simulators. For some cores, only the plain text RTL model is
generated, and you can simulate that model. Use the simulation models only for simulation and
not for synthesis or any other purposes. Using these models for synthesis creates a nonfunctional
design.
Related Information
66
Simulating Altera IP Cores in other EDA Tools
UG-MF9504
2014.12.15
Altera Corporation
LVDS SERDES Transmitter/Receiver IP Cores User Guide