Resource utilization and performance – Altera LVDS SERDES Transmitter / Receiver User Manual

Page 2

Features

Supported devices

Soft clock data recovery (CDR) mode

support

All Arria and Stratix

(2)

series devices.

Note: Altera recommends implementing the Bus LVDS (BLVDS) I/O with user logic, instead of the

ALTLVDS_TX and ALTLVDS_RX IP cores.

Related Information

•

AN 522: Implementing Bus LVDS Interface in Supported Altera Device Families

Resource Utilization and Performance

The Quartus II software configures the PLL according to the settings you apply in the ALTLVDS_RX and

ALTVDS_TX parameter editor. All supported devices provide the option to use an external PLL, which

requires you to enter the appropriate PLL parameters.
When the ALTLVDS_TX and ALTLVDS_RX IP cores are instantiated without the external PLL option,

they use one PLL per instance. During compilation, if directed to do so, the compiler tries to merge PLLs

whenever possible to minimize resource usage.
The Arria, Cyclone, Hardcopy, and Stratix series support the Use Shared PLL(s) for Receiver and

Transmitter option to allow both the ALTLVDS_TX and ALTLVDS_RX IP cores to share a PLL. The

Quartus II software lets the transmitter and receiver share the same PLL when both use identical input

clock sources, identical

pll_areset

sources, identical deserialization factors, and identical output

settings. For example, the Quartus II software displays the following message when the PLL merges

successfully:

Info: Receiver fast PLL
and transmitter fast PLL are
merged
together

The Quartus II software displays the following message when it cannot merge the PLLs for the LVDS

transmitter and receiver pair in the design:

Warning: Can't merge transmitter-only fast PLL
and receiver-only fast PLL
name>

Note: One cause for the warning message is that PLLs that are driven by different clocks cannot be

merged. For PLL merging to happen, the input clocks and the settings on the outputs must be

identical.

Note: To use the LVDS I/O standard in the I/O Bank 1 of Cyclone III and Cyclone IV E devices, ensure

that you set the Configuration device I/O voltage to 2.5 V, or Auto in the Device and Pin Options

dialog box of the Quartus II software.

(2)

CDR is not available in the first generation Stratix device family and the Stratix II device family.

However, soft-CDR is available in all other Stratix series including Stratix GX and Stratix II GX..

Resource Utilization and Performance

UG-MF9504

2014.12.15

Altera Corporation

LVDS SERDES Transmitter/Receiver IP Cores User Guide